公开(公告)号：DE60023002T2

公开(公告)日：2006-07-20

申请号：DE60023002

申请日：2000-02-29

Applicant: INTEL CORP

Inventor： SHAHIDZADEH SHAHROKH ,  BIGBEE E ,  PAPWORTH B ,  BINNS FRANK ,  COLWELL P

IPC: G06F9/34 ,  G06F9/355 ,  G06F9/318 ,  G06F12/02

Abstract: A microprocessor for providing an extended linear address of more than 32 bits. The extended linear address may be provided by concatenating a linear address with a segment selector extension, or by concatenating the values from two registers. Hierarchical translation of a linear address to a physical address is performed in which the number of levels in the hierarchy depends upon whether the linear address is an extended linear address.

公开(公告)号：DE60023002D1

公开(公告)日：2006-02-16

申请号：DE60023002

申请日：2000-02-29

Applicant: INTEL CORP

Inventor： SHAHIDZADEH SHAHROKH ,  BIGBEE E ,  PAPWORTH B ,  BINNS FRANK ,  COLWELL P

IPC: G06F9/34 ,  G06F9/318 ,  G06F9/355 ,  G06F12/02

Abstract: A microprocessor for providing an extended linear address of more than 32 bits. The extended linear address may be provided by concatenating a linear address with a segment selector extension, or by concatenating the values from two registers. Hierarchical translation of a linear address to a physical address is performed in which the number of levels in the hierarchy depends upon whether the linear address is an extended linear address.