-
公开(公告)号：JP2007183950A
公开(公告)日：2007-07-19
申请号：JP2006349809
申请日：2006-12-26
Applicant: Intel Corp , インテル コーポレイション
Inventor： SHAM M DATTA , GREINER ROBERT , BINNS FRANK , KESHAVAN TIRUVALLUR , PARTHASARATHY RAJESH , PARTHASARATHY MADHAVAN
IPC: G06F13/14
CPC classification number: G06F9/342 , G06F9/30174 , G06F12/0292 , G06F12/063 , G06F2212/206
Abstract: PROBLEM TO BE SOLVED: To expand efficiency and performance of a system while maintaining compatibility with legacy OS software. SOLUTION: A device, a system, a method, and a product work for detecting an input/output access action associated with a configuration memory address and a first memory address bit size. In some cases, the configuration memory address and associated configuration data are connected to a packet with a bit size (for example, 64 bit) of a second memory address larger than that (for example, 32 bits) of a first memory address. The packet is used for establishing compatibility with a legacy operating system communicating with a PCI (Peripheral Component Interconnect) interface-based peripheral device and a similar platform device integrated in the same package as a processor. COPYRIGHT: (C)2007,JPO&INPIT
Abstract translation: 要解决的问题：提高系统的效率和性能，同时保持与旧版OS软件的兼容性。 解决方案：用于检测与配置存储器地址和第一存储器地址位大小相关联的输入/输出访问动作的设备，系统，方法和产品工作。 在一些情况下，配置存储器地址和相关联的配置数据被连接到具有大于第一存储器地址（例如，32位）的第二存储器地址的位大小（例如，64位）的分组。 该数据包用于与与基于PCI（外围组件互连）接口的外围设备通信的传统操作系统和与处理器集成在同一封装中的类似平台设备建立兼容性。 版权所有（C）2007，JPO＆INPIT
-
公开(公告)号：JP2005025741A
公开(公告)日：2005-01-27
申请号：JP2004188541
申请日：2004-06-25
Applicant: Intel Corp , インテル コーポレイション
Inventor： COKE JAMES , RUSCITO PETER , TAHIR MASOOD , JACKSON DAVID , NAYDENOV VES , RODGERS DION , TOLL BRET , BINNS FRANK
CPC classification number: G06F9/30149 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30185
Abstract: PROBLEM TO BE SOLVED: To provide an effective method for extending an instruction set without increasing complexity of hardware. SOLUTION: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such that the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant for determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode. COPYRIGHT: (C)2005,JPO&NCIPI
Abstract translation: 要解决的问题：提供扩展指令集而不增加硬件复杂度的有效方法。 公开了一种用于解码可变长度指令集中的指令的方法，装置和系统。 该指令是一组新的指令之一，它使用长度为两个字节的新的转义码值来指示第三个操作码字节包含新指令的指令特定操作码。 定义新指令，使得可以使用相同的一组输入来确定用于新的转义操作码值之一的操作码映射中的每个指令的长度，其中每个输入与确定每个指令的长度有关 新的操作码地图。 对于至少一个实施例，在不评估指令特定操作码的情况下确定新指令之一的长度。 版权所有（C）2005，JPO＆NCIPI
-
公开(公告)号：WO2007078959A3
公开(公告)日：2007-12-21
申请号：PCT/US2006048556
申请日：2006-12-18
Applicant: INTEL CORP , DIXON MARTIN G , KOUFATY DAVID A , RUST CAMRON B , GARTLER HERMANN W , BINNS FRANK
Inventor： DIXON MARTIN G , KOUFATY DAVID A , RUST CAMRON B , GARTLER HERMANN W , BINNS FRANK
IPC: G06F12/14
CPC classification number: G06F12/1425 , G06F12/1491
Abstract: Apparatuses and methods for steering SMM code region accesses are disclosed. In one embodiment, an apparatus includes a status indicator, a base storage location, and an abort storage location. The status indicator is to indicate whether the apparatus is operating in SMM. The base storage location is to store a base address and the abort storage location is to store an abort address. The base address is to specify a first memory address region at which SMM code is to be accessed. The abort address is to specify a second memory address region to which accesses to the first memory address region are to be steered if the apparatus is not operating in SMM.
Abstract translation: 公开了用于转向SMM码区域访问的装置和方法。 在一个实施例中，装置包括状态指示符，基本存储位置和中止存储位置。 状态指示灯是指示设备是否在SMM中运行。 基本存储位置是存储基地址，并且中止存储位置是存储中止地址。 基地址是指定要访问SMM代码的第一个存储器地址区域。 中止地址是指定第二存储器地址区域，如果该设备不在SMM中操作，则对第一存储器地址区域进行访问将被转向。
-
公开(公告)号：WO2011025626A9
公开(公告)日：2011-05-26
申请号：PCT/US2010044089
申请日：2010-08-02
Applicant: INTEL CORP , NATU MAHESH S , GANESAN BASKARAN , RANGARAJAN THANUNATHAN , KUMAR MOHAN J , DOSHI GAUTAM B , PARTHASARATHY RAJESH S , DATTA SHAMMANNA M , BINNS FRANK , MURTHY RAJESH NAGARAJA , SWANSON ROBERT C
Inventor： NATU MAHESH S , GANESAN BASKARAN , RANGARAJAN THANUNATHAN , KUMAR MOHAN J , DOSHI GAUTAM B , PARTHASARATHY RAJESH S , DATTA SHAMMANNA M , BINNS FRANK , MURTHY RAJESH NAGARAJA , SWANSON ROBERT C
IPC: G06F13/10
CPC classification number: G06F13/24 , G06F9/30101 , G06F9/3017 , G06F9/30189 , G06F9/3851 , G06F9/461 , G11C7/1072 , G11C11/40615
Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括处理器，该处理器具有诸如静态随机存取存储器的片上存储器，以存储在进入系统时被交换出处理器的架构状态存储器的一个或多个线程的架构状态 管理模式（SMM）。 通过这种方式，可以避免将此状态信息传送到系统管理存储器，从而减少与进入SMM相关的等待时间。 实施例还可以使得处理器能够更新处于长指令流程或处于系统管理中断（SMI）阻塞状态的执行代理的状态，以便向SMM内的代理提供指示。 描述并要求保护其他实施例。
-
公开(公告)号：WO2011025626A2
公开(公告)日：2011-03-03
申请号：PCT/US2010044089
申请日：2010-08-02
Applicant: INTEL CORP , NATU MAHESH S , GANESAN BASKARAN , RANGARAJAN THANUNATHAN , KUMAR MOHAN J , DOSHI GAUTAM B , PARTHASARATHY RAJESH S , DATTA SHAMMANNA M , BINNS FRANK , MURTHY RAJESH NAGARAJA , SWANSON ROBERT C
Inventor： NATU MAHESH S , GANESAN BASKARAN , RANGARAJAN THANUNATHAN , KUMAR MOHAN J , DOSHI GAUTAM B , PARTHASARATHY RAJESH S , DATTA SHAMMANNA M , BINNS FRANK , MURTHY RAJESH NAGARAJA , SWANSON ROBERT C
IPC: G06F13/10
CPC classification number: G06F13/24 , G06F9/30101 , G06F9/3017 , G06F9/30189 , G06F9/3851 , G06F9/461 , G11C7/1072 , G11C11/40615
Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括具有诸如静态随机存取存储器之类的片上存储器的处理器，用于存储在进入系统时从处理器的架构状态存储器交换的一个或多个线程的架构状态 管理模式（SMM）。 以这种方式，可以避免该状态信息与系统管理存储器的通信，减少与进入SMM相关联的延迟。 实施例还可以使处理器更新处于长指令流或处于系统管理中断（SMI）阻塞状态中的执行代理的状态，以向SMM内的代理提供指示。 描述和要求保护其他实施例。
-
Patent Agency Ranking
公开(公告)号：NL1026490C2
公开(公告)日：2007-10-16
申请号：NL1026490
申请日：2004-06-23
Applicant: INTEL CORP
-
公开(公告)号：GB2510792A
公开(公告)日：2014-08-20
申请号：GB201122094
申请日：2010-08-02
Applicant: INTEL CORP
Inventor： NATU MAHESH S , GANESAN BASKARAN , RANGARAJAN THANUMATHAN , KUMAR MOHAN J , DOSHI GAUTMAN B , PARTHASARATHY RAJESH S , DATTA SHAMMANNA M , BINNS FRANK , MURTHY RAJESH NAGARAJA , SWANSON ROBERT C
IPC: G06F9/48
Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.
-
公开(公告)号：DE102010034555A1
公开(公告)日：2011-03-03
申请号：DE102010034555
申请日：2010-08-17
Applicant: INTEL CORP
-
公开(公告)号：DE112006003132T5
公开(公告)日：2008-09-25
申请号：DE112006003132
申请日：2006-12-18
Applicant: INTEL CORP
Inventor： DIXON MARTIN G , KOUFATY DAVID A , RUST CAMRON B , GARTLER HERMANN W , BINNS FRANK
IPC: G06F12/14
Abstract: Apparatuses and methods for steering SMM code region accesses are disclosed. In one embodiment, an apparatus includes a status indicator, a base storage location, and an abort storage location. The status indicator is to indicate whether the apparatus is operating in SMM. The base storage location is to store a base address and the abort storage location is to store an abort address. The base address is to specify a first memory address region at which SMM code is to be accessed. The abort address is to specify a second memory address region to which accesses to the first memory address region are to be steered if the apparatus is not operating in SMM.
-
公开(公告)号：DE60023002D1
公开(公告)日：2006-02-16
申请号：DE60023002
申请日：2000-02-29
Applicant: INTEL CORP
Inventor： SHAHIDZADEH SHAHROKH , BIGBEE E , PAPWORTH B , BINNS FRANK , COLWELL P
Abstract: A microprocessor for providing an extended linear address of more than 32 bits. The extended linear address may be provided by concatenating a linear address with a segment selector extension, or by concatenating the values from two registers. Hierarchical translation of a linear address to a physical address is performed in which the number of levels in the hierarchy depends upon whether the linear address is an extended linear address.
-
-
-
-
-
-
-
-
-
Search Results
17
records
(took 0.022 seconds)
