公开(公告)号：WO2005017907A3

公开(公告)日：2005-06-02

申请号：PCT/US2004024277

申请日：2004-07-28

Applicant: INTEL CORP ,  LOWREY TYLER ,  PARKINSON WARD

Inventor： LOWREY TYLER ,  PARKINSON WARD

IPC: G11C16/02 ,  G11C11/34

CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/76

Abstract: A read bias scheme may be used for phase change memories including a chalcogenide access device and a chalcogenide memory element. Through an appropriate read bias scheme, desirable read margin can be achieved. This may result in better yield, higher reliability, and ultimately lower costs in some cases.

Abstract translation: 读偏置方案可用于包括硫族化物存取装置和硫族化物存储元件的相变存储器。 通过适当的读取偏置方案，可以实现理想的读取余量。 这可能导致更好的产量，更高的可靠性，并且在某些情况下最终降低成本。

公开(公告)号：DE602005003232T2

公开(公告)日：2008-08-28

申请号：DE602005003232

申请日：2005-06-24

Applicant: INTEL CORP

Inventor： PARKINSON WARD ,  DENNISON CHARLES ,  HUDGENS STEPHEN

IPC: G11C16/02

Abstract: A memory may include a phase change memory element and series connected first and second selection devices. The second selection device may have a higher resistance and a larger threshold voltage than the first selection device. In one embodiment, the first selection device may have a threshold voltage substantially equal to its holding voltage. In some embodiments, the selection devices and the memory element may be made of chalcogenide. In some embodiments, the selection devices may be made of non-programmable chalcogenide. The selection device with the higher threshold voltage may contribute lower leakage to the combination, but may also exhibit increased snapback. This increased snapback may be counteracted by the selection device with the lower threshold voltage, resulting in a combination with low leakage and high performance in some embodiments.

公开(公告)号：AT377830T

公开(公告)日：2007-11-15

申请号：AT05772144

申请日：2005-06-24

Applicant: INTEL CORP

Inventor： PARKINSON WARD ,  DENNISON CHARLES ,  HUDGENS STEPHEN

IPC: G11C16/02

Abstract: A memory may include a phase change memory element and series connected first and second selection devices. The second selection device may have a higher resistance and a larger threshold voltage than the first selection device. In one embodiment, the first selection device may have a threshold voltage substantially equal to its holding voltage. In some embodiments, the selection devices and the memory element may be made of chalcogenide. In some embodiments, the selection devices may be made of non-programmable chalcogenide. The selection device with the higher threshold voltage may contribute lower leakage to the combination, but may also exhibit increased snapback. This increased snapback may be counteracted by the selection device with the lower threshold voltage, resulting in a combination with low leakage and high performance in some embodiments.

公开(公告)号：AT422094T

公开(公告)日：2009-02-15

申请号：AT03734480

申请日：2003-06-09

Applicant: INTEL CORP

Inventor： PARKINSON WARD ,  LOWREY TYLER

IPC: G11C11/00 ,  G11C11/34 ,  G11C16/26 ,  G11C16/34

Abstract: A technique includes determining whether a storage level of a phase change memory cell is within a predefined margin from a resistance threshold. In response to the determination, the cell is selectively written.

公开(公告)号：DE602005003232D1

公开(公告)日：2007-12-20

申请号：DE602005003232

申请日：2005-06-24

Applicant: INTEL CORP

Inventor： PARKINSON WARD ,  DENNISON CHARLES ,  HUDGENS STEPHEN

IPC: G11C16/02

Abstract: A memory may include a phase change memory element and series connected first and second selection devices. The second selection device may have a higher resistance and a larger threshold voltage than the first selection device. In one embodiment, the first selection device may have a threshold voltage substantially equal to its holding voltage. In some embodiments, the selection devices and the memory element may be made of chalcogenide. In some embodiments, the selection devices may be made of non-programmable chalcogenide. The selection device with the higher threshold voltage may contribute lower leakage to the combination, but may also exhibit increased snapback. This increased snapback may be counteracted by the selection device with the lower threshold voltage, resulting in a combination with low leakage and high performance in some embodiments.