公开(公告)号：AU4416496A

公开(公告)日：1996-06-26

申请号：AU4416496

申请日：1995-12-06

Applicant: INTEL CORP

Inventor： KARDACH JAMES ,  CHO SUNG SOO ,  PETERSON NICHOLAS B ,  LANE THOMAS R ,  JOSHI JAYESH M ,  SONGER NEIL

IPC: G06F13/24 ,  G06F9/46 ,  G06F13/14

Abstract: A serial interrupt bus protocol is implemented in which any number of peripherals in a computer system may signal any predetermined interrupt signals to the system's interrupt controller without requiring a dedicated pin for each possible interrupt. Each peripheral implemented on the serial interrupt bus incorporates state machine logic for cycling through possible interrupt states. The peripherals are daisy chained beginning and ending with a serial interrupt controller which follows the same state machine logic as the system peripherals. When the serial interrupt controller receives an active interrupt signal, it determines which interrupt signal to provide to the system's interrupt controller based on the interrupt state of the interrupt controller state machine logic. Peripherals on a secondary serial interrupt bus may be daisy chained with peripherals on a primary system interrupt bus through a system interrupt bridge which also includes state machine logic for following the same state diagram as the system peripherals.

公开(公告)号：BR9508427A

公开(公告)日：1997-11-25

申请号：BR9508427

申请日：1995-12-06

Applicant: INTEL CORP

Inventor： KARDACH JAMES ,  CHO SUNG SOO ,  PETERSON NICHOLAS B ,  LANE THOMAS R ,  JOSHI JAYESH M ,  SONGER NEIL

IPC: G06F13/24 ,  G06F9/46 ,  G06F13/14

Abstract: A serial interrupt bus protocol is implemented in which any number of peripherals in a computer system may signal any predetermined interrupt signals to the system's interrupt controller without requiring a dedicated pin for each possible interrupt. Each peripheral implemented on the serial interrupt bus incorporates state machine logic for cycling through possible interrupt states. The peripherals are daisy chained beginning and ending with a serial interrupt controller which follows the same state machine logic as the system peripherals. When the serial interrupt controller receives an active interrupt signal, it determines which interrupt signal to provide to the system's interrupt controller based on the interrupt state of the interrupt controller state machine logic. Peripherals on a secondary serial interrupt bus may be daisy chained with peripherals on a primary system interrupt bus through a system interrupt bridge which also includes state machine logic for following the same state diagram as the system peripherals.

公开(公告)号：EP2974024A4

公开(公告)日：2016-11-02

申请号：EP14770873

申请日：2014-02-25

Applicant: INTEL CORP

Inventor： HUANG CHOUPIN ,  BODDU VIJAYA K ,  RUSU STEFAN ,  PETERSON NICHOLAS B

IPC: G06F1/04 ,  H03K19/0175 ,  H03L7/07 ,  H03L7/08

CPC classification number: H03L7/07 ,  G06F1/06 ,  G06F1/10 ,  G06F3/167 ,  H03L7/08 ,  H03L7/0891 ,  H03L2207/06

公开(公告)号：EP0796464A4

公开(公告)日：1999-07-28

申请号：EP95943003

申请日：1995-12-06

Applicant: INTEL CORP

Inventor： KARDACH JAMES ,  CHO SUNG SOO ,  PETERSON NICHOLAS B ,  LANE THOMAS R ,  JOSHI JAYESH M ,  SONGER NEIL

IPC: G06F13/24 ,  G06F9/46 ,  G06F13/14

CPC classification number: G06F13/24

Abstract: A serial interrupt bus protocol is implemented in which any number of peripherals in a computer system may signal any predetermined interrupt signals to the system's interrupt controller (22) without requiring a dedicated pin for each possible interrupt. Each peripheral implemented on the serial interrupt bus incorporates state machine logic for cycling through possible interrupt states. The peripherals are daisy chained beginning and ending with a serial interrupt controller (25) which follows the same state machine logic as the sytem peripherals. When the serial interrupt controller (25) receives an active signal, it determines which interrupt signal to provide to the system's interrupt controller (22) based on the interrupt state of the interrupt controller state machine logic. Peripherals (41, 42) on a secondary serial interrupt bus may be daisy chained with peripherals (30, 31, 32) on a primary system interrupt bus through a system interrupt bridge (40) which also includes state machine logic for following the same state diagram as the system peripherals.