公开(公告)号：EP2972878A4

公开(公告)日：2016-11-09

申请号：EP13877966

申请日：2013-03-15

Applicant: INTEL CORP

Inventor： DAUTENHAHN NATHAN ,  GOTTSCHLICH JUSTIN E ,  POKAM GILLES A ,  PEREIRA CRISTIANO L ,  HU SHILIANG ,  DANNE KLAUS ,  KASSA ROLF

IPC: G06F11/36 ,  G06F9/46 ,  G06F11/14 ,  G06F11/34

CPC classification number: G06F9/30145 ,  G06F9/3009 ,  G06F9/3895 ,  G06F9/3897 ,  G06F9/52 ,  G06F11/0724 ,  G06F11/1438 ,  G06F11/1484 ,  G06F11/3636

Abstract: A mechanism is described for facilitating dynamic and efficient management of instruction atomicity violations in software programs according to one embodiment. A method of embodiments, as described herein, includes receiving, at a replay logic from a recording system, a recording of a first software thread running a first macro instruction, and a second software thread running a second macro instruction. The first software thread and the second software thread are executed by a first core and a second core, respectively, of a processor at a computing device. The recording system may record interleavings between the first and second macro instructions. The method includes correctly replaying the recording of the interleavings of the first and second macro instructions precisely as they occurred. The correctly replaying may include replaying a local memory state of the first and second macro instructions and a global memory state of the first and second software threads.

Abstract translation: 一种机制被描述为软件程序雅鼎用于便利指令原子侵犯的动态，高效的管理。 实施例的方法中，如所描述的，包括接收，在从记录系统中，运行的第一宏指令的第一软件线程的记录，并运行一个第二宏指令的第二软件线程的重放逻辑。 所述第一软件线程与第二软件线程由第一芯和一个第二芯在计算设备处执行的分别，一个处理器。 记录系统可以记录在第一和第二宏指令之间的交错。 该方法包括：正确重放的第一和第二个宏指令间剩余物的记录精确地他们发生。 正确重放可以包括重放的第一和第二宏指令本地内存状态并在第一和第二软件线程的全局内存状态。

公开(公告)号：EP3080702A4

公开(公告)日：2017-07-26

申请号：EP13899151

申请日：2013-12-12

Applicant: INTEL CORP

Inventor： HU SHILIANG ,  POKAM GILLES A ,  PEREIRA CRISTIANO L ,  GOTTSCHLICH JUSTIN E

IPC: G06F11/36 ,  G06F11/07 ,  G06F11/30

CPC classification number: G06F11/3632 ,  G06F9/526 ,  G06F11/0715 ,  G06F11/0778 ,  G06F11/366

Abstract: Various embodiments are generally directed to detecting race conditions arising from uncoordinated data accesses by different portions of an application routine by detecting occurrences of a selected cache event associated with such accesses. An apparatus includes a processor component; a trigger component for execution by the processor component to configure a monitoring unit of the processor component to detect a cache event associated with a race condition between accesses to a piece of data and to capture an indication of a state of the processor component to generate monitoring data in response to an occurrence of the cache event; and a counter component for execution by the processor component to configure a counter of the monitoring unit to enable capture of the indication of the state of the processor component at a frequency less than every occurrence of the cache event. Other embodiments are described and claimed.

Abstract translation: 各种实施例通常涉及通过检测与这种访问相关联的所选高速缓存事件的发生来检测由应用程序的不同部分的不协调数据访问引起的竞争状况。 一种设备包括处理器组件; 触发组件，所述触发组件由所述处理器组件执行以配置所述处理器组件的监视单元以检测与对一条数据的访问之间的竞争条件相关联的缓存事件并捕获所述处理器组件的状态的指示以生成监视 响应于高速缓存事件的发生的数据; 以及计数器组件，所述计数器组件由所述处理器组件执行以配置所述监视单元的计数器，以使得能够以低于所述缓存事件的每次发生的频率捕获所述处理器组件的所述状态的所述指示。 描述并要求保护其他实施例。

公开(公告)号：EP3123306A4

公开(公告)日：2017-11-22

申请号：EP15768457

申请日：2015-03-25

Applicant: INTEL CORP

Inventor： CALCIU IRINA ,  GOTTSCHLICH JUSTIN E ,  SHPEISMAN TATIANA ,  POKAM GILLES A

IPC: G06F9/38 ,  G06F9/46 ,  G06F9/52

CPC classification number: G06F9/467 ,  G06F9/528

Abstract: In an embodiment of a transactional memory system, an apparatus includes a processor and an execution logic to enable concurrent execution of at least one first software transaction of a first software transaction mode and a second software transaction of a second software transaction mode and at least one hardware transaction of a first hardware transaction mode and at least one second hardware transaction of a second hardware transaction mode. In one example, the execution logic may be implemented within the processor. Other embodiments are described and claimed.

公开(公告)号：EP2901268A4

公开(公告)日：2016-06-15

申请号：EP13840497

申请日：2013-09-26

Applicant: INTEL CORP

Inventor： GOTTSCHLICH JUSTIN E ,  DANNE KLAUS ,  PEREIRA CRISTIANO L ,  POKAM GILLES A ,  KASSA ROLF ,  HU SHILIANG ,  KRANICH TIM

IPC: G06F9/38 ,  G06F9/44 ,  G06F9/46 ,  G06F9/52 ,  G06F11/34 ,  G06F11/36

CPC classification number: G06F9/3005 ,  G06F9/30072 ,  G06F9/3802 ,  G06F9/3851 ,  G06F9/44 ,  G06F9/455 ,  G06F9/52 ,  G06F11/30 ,  G06F11/3414 ,  G06F11/3476 ,  G06F11/36 ,  G06F11/3664 ,  G06F11/3688 ,  G06F2201/815 ,  G06F2201/825 ,  G06F2201/865

Abstract: Embodiments may provide a method for performing a replay of a previous execution of a program. The method includes generating an order of recorded chunks of instructions across a plurality of recorded threads based, at least in part, on log files generated from the previous execution of the program. The method includes initiating execution of the program, the executing program having a plurality of threads, each thread having a number of chunks of instructions. The method includes intercepting, by a virtual machine unit executing on a processor, an instruction of a chunk before the instruction is executed. The method includes determining, by a replay module executing on the processor, that the chunk is an active chunk if the chunk is currently in line for execution according to the order of recorded chunks, and responsive to a determination that the chunk is the active chunk, executing the instruction.

Abstract translation: 一个或多个实施例可以提供用于执行重放的方法。 该方法包括启动程序的执行，程序具有多组指令，并且每组指令具有多个指令块。 该方法还包括由在处理器上执行的虚拟机单元截取在执行之前块数量的指令。 该方法还包括通过在处理器上执行的重播模块确定该块是否是活动块，并且响应于该块作为活动块来执行该指令。

公开(公告)号：EP3123321A4

公开(公告)日：2017-11-29

申请号：EP15769041

申请日：2015-03-23

Applicant: INTEL CORP

Inventor： GOTTSCHLICH JUSTIN E ,  POKAM GILLES A ,  HU SHILIANG ,  KASSA ROLF ,  WU YOUFENG ,  CALCIU IRINA

IPC: G06F9/455 ,  G06F11/36

CPC classification number: G06F9/467 ,  G06F11/34 ,  G06F11/362 ,  G06F11/3648

Abstract: A system is disclosed that includes a processor and a dynamic random access memory (DRAM). The processor includes a hybrid transactional memory (HyTM) that includes hardware transactional memory (HTM), and a program debugger to replay a program that includes an HTM instruction and that has been executed has been executed using the HyTM. The program debugger includes a software emulator that is to replay the HTM instruction by emulation of the HTM. Other embodiments are disclosed and claimed.

公开(公告)号：EP2972841A4

公开(公告)日：2017-01-11

申请号：EP13878300

申请日：2013-03-13

Applicant: INTEL CORP

Inventor： GOTTSCHLICH JUSTIN E ,  POKAM GILLES A ,  PEREIRA CRISTIANO L ,  DANNE KLAUS ,  SHILIANG HU ,  KASSA ROLF

IPC: G06F9/46 ,  G06F11/32 ,  G06F11/36 ,  G06T1/00

CPC classification number: G06F11/3664 ,  G06F9/38 ,  G06F11/323 ,  G06F11/3404 ,  G06F2201/865 ,  G06T11/206 ,  G06T13/80

Abstract: A system graphically visualizes performance and/or correctness features of a recorded execution of a multi-threaded software program. The system may process chunk-based information recorded during an execution of the multi-threaded program, prepare a graphical visualization of the recorded information, and display the graphical visualization on a display in an animated fashion. The system may allow a viewer to interactively control the display of the animated graphical visualization.

Abstract translation: 一种系统，图形可视化的多线程软件程序的记录执行的性能和/或正确性特征。 该系统可以处理在多线程程序的执行期间记录基于块的信息，准备所记录的信息的图形可视化，并在动画的方式显示在显示器上的图形可视化。 该系统可以允许观看者交互地控制动画图形可视化的显示。