公开(公告)号：WO2011163417A3

公开(公告)日：2012-04-19

申请号：PCT/US2011041527

申请日：2011-06-22

Applicant: INTEL CORP ,  COHEN EHUD ,  MARGULIS OLEG ,  SADE RANNAN ,  SHWARTSMAN STANISLAV

Inventor： COHEN EHUD ,  MARGULIS OLEG ,  SADE RANNAN ,  SHWARTSMAN STANISLAV

IPC: G06F1/32 ,  G06F12/08

CPC classification number: G06F12/0864 ,  G06F12/0859 ,  G06F2212/1028 ,  G06F2212/6082 ,  Y02D10/13

Abstract: A method and system to reduce the power consumption of a memory device. In one embodiment of the invention, the memory device is a N-way set-associative level one (L1) cache memory and there is logic coupled with the data cache memory to facilitate access to only part of the N-ways of the N-way set-associative L1 cache memory in response to a load instruction or a store instruction. By reducing the number of ways to access the N-way set-associative L1 cache memory for each load or store request, the power requirements of the N-way set-associative L1 cache memory is reduced in one embodiment of the invention. In one embodiment of the invention, when a prediction is made that the accesses to cache memory only requires the data arrays of the N-way set-associative L1 cache memory, the access to the fill buffers are deactivated or disabled.

Abstract translation: 一种降低存储器件功耗的方法和系统。 在本发明的一个实施例中，存储器件是N路组合关联级（L1）高速缓冲存储器，并且存在与数据高速缓冲存储器耦合的逻辑，以便于仅访问N- 响应于加载指令或存储指令，单向设置关联L1高速缓冲存储器。 通过减少针对每个加载或存储请求访问N路组合关联的L1高速缓冲存储器的方法的数量，在本发明的一个实施例中，减少了N路组合关联的L1高速缓冲存储器的功率需求。 在本发明的一个实施例中，当预测到对高速缓存存储器的访问仅需要N路组关联的L1高速缓冲存储器的数据阵列时，对填充缓冲器的访问被去激活或禁用。

公开(公告)号：EP2585892A4

公开(公告)日：2014-04-23

申请号：EP11798884

申请日：2011-06-22

Applicant: INTEL CORP

Inventor： COHEN EHUD ,  MARGULIS OLEG ,  SADE RANNAN ,  SHWARTSMAN STANISLAV

IPC: G06F1/32 ,  G06F12/08

CPC classification number: G06F12/0864 ,  G06F12/0859 ,  G06F2212/1028 ,  G06F2212/6082 ,  Y02D10/13

Abstract: A method and system to reduce the power consumption of a memory device. In one embodiment of the invention, the memory device is a N-way set-associative level one (L1) cache memory and there is logic coupled with the data cache memory to facilitate access to only part of the N-ways of the N-way set-associative L1 cache memory in response to a load instruction or a store instruction. By reducing the number of ways to access the N-way set-associative L1 cache memory for each load or store request, the power requirements of the N-way set-associative L1 cache memory is reduced in one embodiment of the invention. In one embodiment of the invention, when a prediction is made that the accesses to cache memory only requires the data arrays of the N-way set-associative L1 cache memory, the access to the fill buffers are deactivated or disabled.