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    EXTENDING CACHE COHERENCY PROTOCOLS TO SUPPORT LOCALLY BUFFERED DATA
    1.
    发明申请
    EXTENDING CACHE COHERENCY PROTOCOLS TO SUPPORT LOCALLY BUFFERED DATA 审中-公开
    扩展缓存协议来支持本地缓存数据

    公开(公告)号：WO2010077885A3

    公开(公告)日：2010-10-07

    申请号：PCT/US2009068121

    申请日：2009-12-15

    Applicant: INTEL CORP ,  SHEAFFER GAD ,  RAIKIN SHLOMO ,  BASSIN VADIM ,  COHEN EHUD ,  MARGULIS OLEG ,  SADE RAANAN

    Inventor： SHEAFFER GAD ,  RAIKIN SHLOMO ,  BASSIN VADIM ,  COHEN EHUD ,  MARGULIS OLEG ,  SADE RAANAN

    IPC: G06F9/06 ,  G06F5/00 ,  G06F9/46 ,  G06F12/00

    CPC classification number: G06F9/3834 ,  G06F9/467 ,  G06F12/0831 ,  G06F12/084

    Abstract: A method and apparatus for extending cache coherency to hold buffered data to support transactional execution is herein described. A transactional store operation referencing an address associated with a data item is performed in a buffered manner. Here, the coherency state associated with cache lines to hold the data item are transitioned to a buffered state. In response to local requests for the buffered data item, the data item is provided to ensure internal transactional sequential ordering. However, in response to external access requests, a miss response is provided to ensure the transactionally updated data item is not made globally visible until commit. Upon commit, the buffered lines are transitioned to a modified state to make the data item globally visible.

    Abstract translation: 这里描述了用于扩展高速缓存一致性以保存缓冲数据以支持事务执行的方法和装置。 以缓冲的方式执行引用与数据项相关联的地址的事务存储操作。 这里，与保存数据项的高速缓存行相关联的一致性状态被转换到缓冲状态。 响应缓冲数据项的本地请求，提供数据项以确保内部事务顺序排序。 然而，响应于外部访问请求，提供了错误响应以确保事务更新的数据项在提交之前不会被全局可见。 一旦提交，缓存的行将转换到修改状态，使数据项全局可见。

    METAPHYSICAL ADDRESS SPACE FOR HOLDING LOSSY METADATA IN HARDWARE
    2.
    发明申请
    METAPHYSICAL ADDRESS SPACE FOR HOLDING LOSSY METADATA IN HARDWARE 审中-公开
    用于在硬件中保存损失元数据的地形空间

    公开(公告)号：WO2010077842A2

    公开(公告)日：2010-07-08

    申请号：PCT/US2009067983

    申请日：2009-12-15

    Applicant: INTEL CORP ,  SHAEFFER GAD ,  RAIKIN SHLOMO ,  BASSIN VADIM ,  SADE RAANAN ,  COHEN EHUD ,  MARGULIS OLEG

    Inventor： SHAEFFER GAD ,  RAIKIN SHLOMO ,  BASSIN VADIM ,  SADE RAANAN ,  COHEN EHUD ,  MARGULIS OLEG

    IPC: G06F9/06 ,  G06F9/46 ,  G06F12/00

    CPC classification number: G06F12/0615 ,  G06F9/467 ,  G06F12/0842 ,  G06F12/1027

    Abstract: A method and apparatus for metaphysical address space for holding lossy metadata is herein described. An explicit or implicit metadata access operation referencing data address of a data item is encountered. Hardware modifies the data address to a metadata address including a metaphysical extension. The metaphysical extension overlays one or more metaphysical address space(s) on the data address space. A portion of the metadata address including the metaphysical extension is utilized to search a tag array of the cache memory holding the data item. As a result, metadata access operations only hit metadata entries of the cache based on the metadata address extension. However, as the metadata is held within the cache, the metadata potentially competes with data for space within the cache.

    Abstract translation: 这里描述用于保存有损元数据的形而上学地址空间的方法和装置。 遇到引用数据项的数据地址的显式或隐式元数据访问操作。 硬件将数据地址修改为包括形而上学扩展的元数据地址。 形而上学扩展覆盖了数据地址空间上的一个或多个形而上学地址空间。 使用包括形而上学扩展的元数据地址的一部分来搜索保存数据项的高速缓冲存储器的标签阵列。 因此，元数据访问操作仅基于元数据地址扩展名来命中高速缓存的元数据条目。 然而，随着元数据被保存在高速缓存中，元数据可能与高速缓存中的空间的数据竞争。

    METHOD AND APPARATUS FOR RECOVERING FROM BAD STORE-TO-LOAD FORWARDING IN AN OUT-OF-ORDER PROCESSOR
    4.
    发明申请
    METHOD AND APPARATUS FOR RECOVERING FROM BAD STORE-TO-LOAD FORWARDING IN AN OUT-OF-ORDER PROCESSOR 审中-公开
    用于在失序处理器中恢复坏的存储负载的方法和设备

    公开(公告)号：WO2017112361A3

    公开(公告)日：2017-07-27

    申请号：PCT/US2016063890

    申请日：2016-11-28

    Applicant: INTEL CORP

    Inventor： MEKKAT VINEETH ,  MARGULIS OLEG ,  AGRON JASON M ,  SCHUCHMAN ETHAN ,  WINKEL SEBASTIAN ,  WU YOUFENG ,  DANKEL GISLE

    IPC: G06F9/30 ,  G06F9/38 ,  G06F11/00 ,  G06F11/07

    CPC classification number: G06F9/30185 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3865

    Abstract: Embodiments of apparatus and methods for detecting and recovering from incorrect memory dependence speculation in an out-of-order processor are described herein. For example, one embodiment of a method comprises: executing a first load instruction; detecting when the first load instruction experiences a bad store-to-load forwarding event during execution; tracking the occurrences of bad store-to-load forwarding event experienced by the first load instruction during execution; controlling enablement of an S-bit in the first load instruction based on the tracked occurrences; generating a plurality of load operations responsive to an enabled S-bit in first load instruction, wherein execution of the plurality of load operations produces a result equivalent to that from the execution of the first load instruction.

    Abstract translation: 这里描述了用于在无序处理器中检测并从不正确的存储器依赖性推测中恢复的设备和方法的实施例。 例如，方法的一个实施例包括：执行第一加载指令; 检测何时第一加载指令在执行期间经历了不良的存储 - 加载转发事件; 跟踪在执行期间由第一加载指令经历的不良存储 - 加载转发事件的发生; 基于所跟踪的事件来控制所述第一加载指令中的S位的启用; 响应于第一加载指令中的启用的S位产生多个加载操作，其中所述多个加载操作的执行产生与来自所述第一加载指令的执行的结果相等的结果。

    METHOD AND SYSTEM TO REDUCE THE POWER CONSUMPTION OF A MEMORY DEVICE
    5.
    发明申请
    METHOD AND SYSTEM TO REDUCE THE POWER CONSUMPTION OF A MEMORY DEVICE 审中-公开
    降低存储器件功耗的方法和系统

    公开(公告)号：WO2011163417A3

    公开(公告)日：2012-04-19

    申请号：PCT/US2011041527

    申请日：2011-06-22

    Applicant: INTEL CORP ,  COHEN EHUD ,  MARGULIS OLEG ,  SADE RANNAN ,  SHWARTSMAN STANISLAV

    Inventor： COHEN EHUD ,  MARGULIS OLEG ,  SADE RANNAN ,  SHWARTSMAN STANISLAV

    IPC: G06F1/32 ,  G06F12/08

    CPC classification number: G06F12/0864 ,  G06F12/0859 ,  G06F2212/1028 ,  G06F2212/6082 ,  Y02D10/13

    Abstract: A method and system to reduce the power consumption of a memory device. In one embodiment of the invention, the memory device is a N-way set-associative level one (L1) cache memory and there is logic coupled with the data cache memory to facilitate access to only part of the N-ways of the N-way set-associative L1 cache memory in response to a load instruction or a store instruction. By reducing the number of ways to access the N-way set-associative L1 cache memory for each load or store request, the power requirements of the N-way set-associative L1 cache memory is reduced in one embodiment of the invention. In one embodiment of the invention, when a prediction is made that the accesses to cache memory only requires the data arrays of the N-way set-associative L1 cache memory, the access to the fill buffers are deactivated or disabled.

    Abstract translation: 一种降低存储器件功耗的方法和系统。 在本发明的一个实施例中，存储器件是N路组合关联级（L1）高速缓冲存储器，并且存在与数据高速缓冲存储器耦合的逻辑，以便于仅访问N- 响应于加载指令或存储指令，单向设置关联L1高速缓冲存储器。 通过减少针对每个加载或存储请求访问N路组合关联的L1高速缓冲存储器的方法的数量，在本发明的一个实施例中，减少了N路组合关联的L1高速缓冲存储器的功率需求。 在本发明的一个实施例中，当预测到对高速缓存存储器的访问仅需要N路组关联的L1高速缓冲存储器的数据阵列时，对填充缓冲器的访问被去激活或禁用。

    READ AND WRITE MONITORING ATTRIBUTES IN TRANSACTIONAL MEMORY (TM) SYSTEMS
    6.
    发明申请
    READ AND WRITE MONITORING ATTRIBUTES IN TRANSACTIONAL MEMORY (TM) SYSTEMS 审中-公开
    TRANSACTIONAL MEMORY（TM）系统中的读取和写入监视属性

    公开(公告)号：WO2010077850A2

    公开(公告)日：2010-07-08

    申请号：PCT/US2009068004

    申请日：2009-12-15

    Applicant: INTEL CORP ,  SHAEFFER GAD ,  RAIKIN SHLOMO ,  BASSIN VADIM ,  SADE RAANAN ,  COHEN EHUD ,  MARGULIS OLEG

    Inventor： SHAEFFER GAD ,  RAIKIN SHLOMO ,  BASSIN VADIM ,  SADE RAANAN ,  COHEN EHUD ,  MARGULIS OLEG

    IPC: G06F12/00 ,  G06F11/30 ,  G06F12/08 ,  G06F13/16

    CPC classification number: G06F12/0831 ,  G06F12/084

    Abstract: A method and apparatus for monitoring memory accesses in hardware to support transactional execution is herein described. Attributes are monitor accesses to data items without regard for detection at physical storage structure granularity, but rather ensuring monitoring at least at data items granularity. As an example, attributes are added to state bits of a cache to enable new cache coherency states. Upon a monitored memory access to a data item, which may be selectively determined, coherency states associated with the data item are updated to a monitored state. As a result, invalidating requests to the data item are detected through combination of the request type and the monitored coherency state of the data item.

    Abstract translation: 这里描述了用于监视硬件中的存储器访问以支持事务执行的方法和设备。 属性是监视器对数据项的访问，不考虑物理存储结构粒度上的检测，而是确保至少在数据项粒度上进行监视。 作为示例，将属性添加到缓存的状态位以启用新的缓存一致性状态。 在受监控的存储器访问可以选择性确定的数据项时，与该数据项相关联的一致性状态被更新为监控状态。 结果，通过组合数据项的请求类型和监视的一致性状态来检测对数据项的无效请求。

    A 2-D GATHER INSTRUCTION AND A 2-D CACHE
    7.
    发明申请
    A 2-D GATHER INSTRUCTION AND A 2-D CACHE 审中-公开
    2-D GATHER指令和2-D缓存

    公开(公告)号：WO2013032788A2

    公开(公告)日：2013-03-07

    申请号：PCT/US2012051748

    申请日：2012-08-21

    Applicant: INTEL CORP ,  GINZBURG BORIS ,  MARGULIS OLEG

    Inventor： GINZBURG BORIS ,  MARGULIS OLEG

    IPC: G06F9/06 ,  G06F9/30 ,  G06T1/00

    CPC classification number: G06F12/0875 ,  G06F2212/452 ,  G06T1/60

    Abstract: A processor may support a two-dimensional (2-D) gather instruction and a 2-D cache. The processor may perform the 2-D gather instruction to access one or more sub-blocks of data from a two-dimensional (2-D) image stored in a memory coupled to the processor. The two-dimensional (2-D) cache may store the sub-blocks of data in a multiple cache lines. Further, the 2-D cache may support access of more than one cache lines while preserving a two-dimensional structure of the 2-D image.

    Abstract translation: 处理器可以支持二维（2-D）采集指令和2-D缓存。 处理器可以执行2-D收集指令以从存储在耦合到处理器的存储器中的二维（2-D）图像访问数据的一个或多个子块。 二维（2-D）高速缓存可以将数据子块存储在多个高速缓存行中。 此外，2-D缓存可以支持多个缓存行的访问，同时保留二维图像的二维结构。

    METHOD AND SYSTEM TO REDUCE THE POWER CONSUMPTION OF A MEMORY DEVICE
    9.
    发明公开
    METHOD AND SYSTEM TO REDUCE THE POWER CONSUMPTION OF A MEMORY DEVICE 审中-公开
    方法和系统以减少电力使用的存储设备

    公开(公告)号：EP2585892A4

    公开(公告)日：2014-04-23

    申请号：EP11798884

    申请日：2011-06-22

    Applicant: INTEL CORP

    Inventor： COHEN EHUD ,  MARGULIS OLEG ,  SADE RANNAN ,  SHWARTSMAN STANISLAV

    IPC: G06F1/32 ,  G06F12/08

    CPC classification number: G06F12/0864 ,  G06F12/0859 ,  G06F2212/1028 ,  G06F2212/6082 ,  Y02D10/13

    Abstract: A method and system to reduce the power consumption of a memory device. In one embodiment of the invention, the memory device is a N-way set-associative level one (L1) cache memory and there is logic coupled with the data cache memory to facilitate access to only part of the N-ways of the N-way set-associative L1 cache memory in response to a load instruction or a store instruction. By reducing the number of ways to access the N-way set-associative L1 cache memory for each load or store request, the power requirements of the N-way set-associative L1 cache memory is reduced in one embodiment of the invention. In one embodiment of the invention, when a prediction is made that the accesses to cache memory only requires the data arrays of the N-way set-associative L1 cache memory, the access to the fill buffers are deactivated or disabled.

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