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    Transparent system interrupts with automatic input/output trap restart
    4.
    发明专利
    Transparent system interrupts with automatic input/output trap restart 未知

    公开(公告)号：GB2259166A

    公开(公告)日：1993-03-03

    申请号：GB9217580

    申请日：1992-08-19

    Applicant: INTEL CORP

    Inventor： KARDACH JAMES ,  NGUYEN CAU ,  SIVAMANI KAMESWARAN

    IPC: G06F9/46 ,  G06F9/48

    Abstract: A CPU of a microprocessor system is modified to post an executed write I/O instruction upon completion of writing by a bus unit. A dedicated memory area (SMRAM) is provided for storing a customizable system interrupt service routine, and for storing at the time of interruption, 102-107, state data of the CPU and an I/O trap indicator indicating the CPU was interrupted during execution of an I/O instruction. The dedicated memory area is normally not mapped as part of the main memory space, thereby keep it inaccessible to the operating system and applications. An unmaskable system supervisor interrupt (SSI) having higher priority than all other maskable and unmaskable interrupts is added to the CPU interrupts. A RESUME instruction is added to the CPU instructions to provide, by use of the stored data and indicator, 112-118, recovery of the CPU to the state before it was interrupted and automatic re-execution of an interrupted I/O instruction. As a result, a system integrator or OEM may provide transparent system level interrupts with automated I/O trap restart that will operate reliably in any operating environment, and be relieved of the heavy burden of managing I/O trap restart.

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