公开(公告)号：EP3238046A4

公开(公告)日：2018-07-18

申请号：EP15873974

申请日：2015-11-23

Applicant: INTEL CORP

Inventor： LAI PATRICK P ,  SONDAG TYLER N ,  WINKEL SEBASTIAN ,  XEKALAKIS POLYCHRONIS ,  SCHUCHMAN ETHAN

IPC: G06F9/38 ,  G06F7/57 ,  G06F9/30

CPC classification number: G06F9/455 ,  G06F9/3001 ,  G06F9/30021 ,  G06F9/30058 ,  G06F9/3017

Abstract: In one embodiment a binary translation is used to fuse multiple macroinstructions of an instruction set architecture into a single macroinstruction. Fusible instruction sequences include a sequence of increment, compare, and jump instructions. In one embodiment, a processing device provides support for the fused macroinstruction. In one embodiment, the processing device executes the fused macroinstruction within a single execution stage of a processor pipeline. In one embodiment, the fused macroinstruction is performed within a single execution cycle.