公开(公告)号：WO2013101078A8

公开(公告)日：2013-09-06

申请号：PCT/US2011067865

申请日：2011-12-29

Applicant: INTEL CORP ,  GIBERT CODINA ENRIC ,  LATORRE FERNANDO ,  CODINA JOSEP M ,  GOMEZ REQUENA CRISPIN ,  GONZALEZ ANTONIO ,  HYUSEINOVA MEYREM ,  KOTSELIDIS CHRISTOS E ,  LOPEZ PEDRO ,  LUPON MARC ,  MADRILES CARLOS ,  MAGKLIS GRIGORIOS ,  MARCUELLO PEDRO ,  MARTINEZ VICENTE ALEJANDRO ,  MARTINEZ RAUL ,  ORTEGA DANIEL ,  PAVLOU DEMOS ,  STAVROU KYRIAKOS A ,  TOURNAVITIS GEORGIOS ,  XEKALAKIS POLYCHRONIS

Inventor： GIBERT CODINA ENRIC ,  LATORRE FERNANDO ,  CODINA JOSEP M ,  GOMEZ REQUENA CRISPIN ,  GONZALEZ ANTONIO ,  HYUSEINOVA MEYREM ,  KOTSELIDIS CHRISTOS E ,  LOPEZ PEDRO ,  LUPON MARC ,  MADRILES CARLOS ,  MAGKLIS GRIGORIOS ,  MARCUELLO PEDRO ,  MARTINEZ VICENTE ALEJANDRO ,  MARTINEZ RAUL ,  ORTEGA DANIEL ,  PAVLOU DEMOS ,  STAVROU KYRIAKOS A ,  TOURNAVITIS GEORGIOS ,  XEKALAKIS POLYCHRONIS

IPC: G06F9/06 ,  G06F12/08

CPC classification number: G06F12/0815 ,  G06F2212/507

Abstract: Techniques are described for providing an enhanced cache coherency protocol for a multi-core processor that includes a Speculative Request For Ownership Without Data (SRFOWD) for a portion of cache memory. With a SRFOWD, only an acknowledgement message may be provided as an answer to a requesting core. The contents of the affected cache line are not required to be a part of the answer. The enhanced cache coherency protocol may assure that a valid copy of the current cache line exists in case of misspeculation by the requesting core. Thus, an owner of the current copy of the cache line may maintain a copy of the old contents of the cache line. The old contents of the cache line may be discarded if speculation by the requesting core turns out to be correct. Otherwise, in case of misspeculation by the requesting core, the old contents of the cache line may be set back to a valid state.

Abstract translation: 描述了用于为多核处理器提供增强的高速缓存一致性协议的技术，所述多核处理器包括用于高速缓冲存储器的一部分的无数据的所有权投标请求（SRFOWD）。 使用SRFOWD，可以仅提供确认消息作为请求内核的答案。 受影响的缓存行的内容不需要作为答案的一部分。 增强的高速缓存一致性协议可以确保在请求核心的错误配置的情况下存在当前高速缓存行的有效副本。 因此，高速缓存行的当前副本的所有者可以维护高速缓存行的旧内容的副本。 如果请求的核心的猜测证明是正确的，则可以丢弃该高速缓存行的旧内容。 否则，在请求核心发生错误的情况下，可以将高速缓存行的旧内容设置回有效状态。

公开(公告)号：DE102015002383A1

公开(公告)日：2015-10-01

申请号：DE102015002383

申请日：2015-02-25

Applicant: INTEL CORP

Inventor： KHARTIKOV DENIS M ,  NEELAKANTAM NAVEEN ,  XEKALAKIS POLYCHRONIS ,  KELM JOHN H

IPC: G06F9/38

Abstract: Hardware/Software-Co-Entwurf für eine optimierte dynamische Out-of-order-Pipeline mit Very Long Instruction Words (VLIW-Pipeline). Zum Beispiel umfasst eine Ausführungsform einer Vorrichtung Folgendes: eine Befehlsabrufeinheit zum Abrufen von Very Long Instruction Words (VLIWs) in ihrer Programmreihenfolge aus dem Speicher, wobei jedes der VLIWs mehrere Reduced-Instruction-Set-Computing-Befehlssilben (RISC-Befehlssilben) umfasst, die in den VLIWs in einer Reihenfolge gruppiert sind, die Datenflussabhängigkeiten und falsche Ausgabeabhängigkeiten zwischen den Silben beseitigt; eine Decodiereinheit zum Decodieren der VLIWs in ihrer Programmreihenfolge und zum parallelen Ausgeben der Silben jedes decodierten VLIW; und eine Out-of-order-Ausführungsmaschine zum vorzugsweise parallelen Ausführen der Silben mit anderen Silben, wobei wenigstens einige der Silben in einer anderen Reihenfolge als der Reihenfolge, in der sie von der Decodiereinheit empfangen werden, ausgeführt werden sollen, wobei die Out-of-order-Ausführungsmaschine eine oder mehrere Verarbeitungsstufen aufweist, die, wenn sie Operationen ausführen, nicht auf Datenflussabhängigkeiten und falsche Ausgabeabhängigkeiten zwischen den Silben prüfen.

公开(公告)号：GB2524619A

公开(公告)日：2015-09-30

申请号：GB201500942

申请日：2015-01-20

Applicant: INTEL CORP

Inventor： KHARTIKOV DENIS M ,  NEELAKANTAM NAVEEN ,  KELM JOHN H ,  XEKALAKIS POLYCHRONIS

IPC: G06F9/38

Abstract: An apparatus comprises: an instruction fetch unit to fetch very long instruction words (VLIWs) in program order from memory, each of the VLIWs comprising a plurality of reduced instruction set computing (RISC) instruction syllables grouped into the VLIWs in an order which removes data-flow dependencies, or read after write hazards, and false output dependencies, or write after write hazards, between the syllables; a decode unit 1501 to decode the VLIWs in program order and output the syllables of each decoded VLIW in parallel; and an out-of-order execution engine 1502-1507 to execute at least some of the syllables in parallel with other syllables, where at least some of the syllables are to be executed in a different order than the order in which they are received from the decode unit, the out-of-order execution engine having one or more processing stages which do not check for data-flow dependencies and false output dependencies between the syllables when performing operations.

公开(公告)号：EP3234767A4

公开(公告)日：2018-07-18

申请号：EP15870563

申请日：2015-11-16

Applicant: INTEL CORP

Inventor： COLLINS JAMISON D ,  IYER JAYESH ,  WINKEL SEBASTIAN ,  XEKALAKIS POLYCHRONIS ,  CHEN HOWARD H ,  BRAUCH RUPERT

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30134 ,  G06F8/41 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/384 ,  G06F9/3859 ,  G06F9/3863

Abstract: Embodiments of a method and apparatus for implementing and maintaining a stack of predicate values with stack synchronization instructions. In one embodiment the apparatus is an out of order hardware/software co-designed processor including instructions to explicitly manage the predicate register stack to maintain stack consistency across branches of executing that push a variable number of predicate values onto the predicate stack. In one embodiment the stack-based predicate register implementation enables early branch calculation and early branch misprediction recovery via early renaming of predicate registers.

公开(公告)号：EP3238046A4

公开(公告)日：2018-07-18

申请号：EP15873974

申请日：2015-11-23

Applicant: INTEL CORP

Inventor： LAI PATRICK P ,  SONDAG TYLER N ,  WINKEL SEBASTIAN ,  XEKALAKIS POLYCHRONIS ,  SCHUCHMAN ETHAN

IPC: G06F9/38 ,  G06F7/57 ,  G06F9/30

CPC classification number: G06F9/455 ,  G06F9/3001 ,  G06F9/30021 ,  G06F9/30058 ,  G06F9/3017

Abstract: In one embodiment a binary translation is used to fuse multiple macroinstructions of an instruction set architecture into a single macroinstruction. Fusible instruction sequences include a sequence of increment, compare, and jump instructions. In one embodiment, a processing device provides support for the fused macroinstruction. In one embodiment, the processing device executes the fused macroinstruction within a single execution stage of a processor pipeline. In one embodiment, the fused macroinstruction is performed within a single execution cycle.

公开(公告)号：EP2798470A4

公开(公告)日：2015-07-15

申请号：EP11878987

申请日：2011-12-29

Applicant: INTEL CORP

Inventor： STAVROU KYRIAKOS A ,  GIBERT CODINA ENRIC ,  CODINA JOSEP M ,  GOMEZ REQUENA CRISPIN ,  GONZALEZ ANTONIO ,  HYUSEINOVA MIREM ,  KOTSELIDIS CHRISTOS E ,  LATORRE FERNANDO ,  LOPEZ PEDRO ,  LUPON MARC ,  MADRILES CARLOS ,  MAGKLIS GRIGORIOS ,  MARCUELLO PEDRO ,  MARTINEZ VICENTE ALEJANDRO ,  MARTINEZ RAUL ,  ORTEGA DANIEL ,  PAVLOU DEMOS ,  TOURNAVITIS GEORGIOS ,  XEKALAKIS POLYCHRONIS

IPC: G06F9/06 ,  G06F9/30

CPC classification number: G06F9/3804 ,  G06F9/30047 ,  G06F9/3017 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3848 ,  G06F12/0862 ,  G06F2212/452

Abstract: Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: identifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache.

Abstract translation: 公开了一种用于从指令高速缓存管理指令高速缓存预取的装置和方法。 处理器可以包括：预取引擎; 预测分支结果的分支预测引擎; 和动态优化器。 动态优化器可用于控制：识别公共指令高速缓存未命中，并将预取引擎的预取指令插入指令高速缓存。

公开(公告)号：EP2798520A4

公开(公告)日：2016-12-07

申请号：EP11878906

申请日：2011-12-29

Applicant: INTEL CORP

Inventor： MAGKLIS GRIGORIOS ,  CODINA JOSEP M ,  ZILLES CRAIG B ,  NEILLY MICHAEL ,  SAMUDRALA SRIDHAR ,  MARTINEZ VICENTE ALEJANDRO ,  XEKALAKIS POLYCHRONIS ,  SANCHEZ F JESUS ,  LUPON MARC ,  TOURNAVITIS GEORGIOS ,  GIBERT CODINA ENRIC ,  GOMEZ REQUENA CRISPIN ,  GONZALEZ ANTONIO ,  HYUSEINOVA MIREM ,  KOTSELIDIS CHRISTOS E ,  LATORRE FERNANDO ,  LOPEZ PEDRO ,  MADRILES CARLOS ,  MARCUELLO PEDRO ,  MARTINEZ RAUL ,  ORTEGA DANIEL ,  PAVLOU DEMOS ,  STAVROU KYRIAKOS A

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3001 ,  G06F9/30032 ,  G06F9/30087 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/3842