公开(公告)号：MY187240A

公开(公告)日：2021-09-13

申请号：MYPI2014703031

申请日：2014-10-14

Applicant: INTEL CORP

Inventor： PENG LIANG ,  SPANGLER STEVEN ,  HAREL YOAV

IPC: G06T1/60 ,  G06T11/00 ,  G06T15/04 ,  G09G5/00

Abstract: Texture filter logic suitable for determining a minimum or maximum texel value from a plurality of texel values associated with a filter footprint of arbitrary shape and size. In embodiments, logic circuitry includes a plurality of min/max comparison block stages (1305, 1306, 1307, 1308, 1315, 1316, 1317, 1318, 1321, 1322, 1331, 1332, 1381) is configured to perform comparisons and determine a min/max value of predetermined number of texel groups. In embodiments, the logic circuitry further includes a number of min/max collectors (1360, 1365, 1370, 1375) to accommodate filter footprints having more texel groups than the predetermined number accommodated by the min/max comparison block stages. Iterative comparisons may be performed until all texel groups in the given footprint have been compared. In further embodiments, the logic circuitry outputs four min/max texel values, which may then be further processed with a final comparison stages to arrive at one min/max value for a footprint.