公开(公告)号：GB2445909A

公开(公告)日：2008-07-23

申请号：GB0809458

申请日：2006-12-07

Applicant: INTEL CORP

Inventor： YIGSAW THEODROS ,  SANTHANAKRISHNAN GEEYARPURAM ,  ROWLAND MARTIN T ,  SRINIVASA GANAPATI

IPC: G06F12/08

Abstract: According to one embodiment of the invention, a method is disclosed for selecting a first subset of a plurality of cache ways in a cache for storing hardware threads identified as high priority hardware threads for processing by a multi-threaded processor in communication with the cache; assigning high priority hardware threads to the selected first subset; monitoring a cache usage of a high priority hardware thread assigned to the selected first subset of plurality of cache ways; and reassigning the assigned high priority hardware thread to any cache way of the plurality of cache ways if the cache usage of the high priority hardware thread exceeds a predetermined inactive cache usage threshold value based on the monitoring.

公开(公告)号：GB2411986B

公开(公告)日：2007-06-20

申请号：GB0502576

申请日：2005-02-08

Applicant: INTEL CORP

Inventor： SHANNON CHRISTOPHER ,  SRINIVASA GANAPATI ,  ROWLAND MARK

IPC: G06F12/08 ,  C07C201/08 ,  C07C201/16 ,  C07C205/06 ,  C07C205/11 ,  G06F12/12

Abstract: A cache line replacement protocol for selecting a cache line for replacement based at least in part on the inter-cache traffic generated as a result of the cache line being replaced.

公开(公告)号：GB2411986A

公开(公告)日：2005-09-14

申请号：GB0502576

申请日：2005-02-08

Applicant: INTEL CORP

Inventor： SHANNON CHRISTOPHER ,  SRINIVASA GANAPATI ,  ROWLAND MARK

IPC: C07C201/08 ,  C07C201/16 ,  C07C205/06 ,  C07C205/11 ,  G06F12/12 ,  G06F12/08

Abstract: A method for replacing a line in a configuration with multiple levels of cache memories, assigning a state for at least one cache line in at least two ways, and assigning a relative cost function for intercache traffic for the state of the cache line associated with replacing the cache line. The cache line can be selected for replacement based at least in part of the cost function. The cache line replacement protocol can be a three bit pseudo random protocol.

公开(公告)号：GB2445909B

公开(公告)日：2011-04-27

申请号：GB0809458

申请日：2006-12-07

Applicant: INTEL CORP

Inventor： YIGSAW THEODROS ,  SANTHANAKRISHNAN GEEYARPURAM ,  ROWLAND MARTIN T ,  SRINIVASA GANAPATI

IPC: G06F12/08

Abstract: According to one embodiment of the invention, a method is disclosed for selecting a first subset of a plurality of cache ways in a cache for storing hardware threads identified as high priority hardware threads for processing by a multi-threaded processor in communication with the cache; assigning high priority hardware threads to the selected first subset; monitoring a cache usage of a high priority hardware thread assigned to the selected first subset of plurality of cache ways; and reassigning the assigned high priority hardware thread to any cache way of the plurality of cache ways if the cache usage of the high priority hardware thread exceeds a predetermined inactive cache usage threshold value based on the monitoring.

公开(公告)号：GB2450281B

公开(公告)日：2011-04-06

申请号：GB0818601

申请日：2007-03-13

Applicant: INTEL CORP

Inventor： MOZAK CHRISTOPHER P ,  GILBERT JEFFREY ,  SRINIVASA GANAPATI

IPC: G06F15/78 ,  G06F13/12

Abstract: In one embodiment, the present invention includes a processor having multiple processor cores to execute instructions, with each of the cores including dedicated digital interface circuitry. The processor further includes an analog interface coupled to the cores via the digital interface circuitry. The analog interface may be used to communicate traffic between a package including the cores and an interconnect such as a shared bus coupled thereto. Other embodiments are described and claimed.

公开(公告)号：DE112007000443B4

公开(公告)日：2015-04-16

申请号：DE112007000443

申请日：2007-03-13

Applicant: INTEL CORP

Inventor： MOZAK CHRISTOPHER ,  GILBERT JEFFREY ,  SRINIVASA GANAPATI

IPC: G06F13/12 ,  G06F13/10 ,  G06F13/20

Abstract: Bei einer Ausführungsform umfasst die vorliegende Erfindung einen Prozessor mit mehreren Prozessorkernen. um Befehle auszuführen, wobei jeder der Kerne eine ihm zugeordnete digitale Schnittstellenschaltung umfasst. Der Prozessor umfasst weiter eine analoge Schnittstelle, die über die digitale Schnittstellenschaltung mit den Kernen gekoppelt ist. Die analoge Schnittstelle kann verwendet werden, um Verkehr zwischen einer Baugruppe. welche die Kerne umfasst, und einer Verbindung. so wie einem gemeinsam genutzten Bus, der an diese gekoppelt ist, zu kommunizieren. Weitere Ausführungsformen sind beschrieben und beansprucht.

公开(公告)号：GB2450281A

公开(公告)日：2008-12-17

申请号：GB0818601

申请日：2007-03-13

Applicant: INTEL CORP

Inventor： MOZAK CHRISTOPHER P ,  GILBERT JEFFREY ,  SRINIVASA GANAPATI

IPC: G06F13/12 ,  G06F13/10 ,  G06F13/20

Abstract: In one embodiment, the present invention includes a processor having multiple processor cores to execute instructions, with each of the cores including dedicated digital interface circuitry. The processor further includes an analog interface coupled to the cores via the digital interface circuitry. The analog interface may be used to communicate traffic between a package including the cores and an interconnect such as a shared bus coupled thereto. Other embodiments are described and claimed.

公开(公告)号：DE112007000443T5

公开(公告)日：2008-12-11

申请号：DE112007000443

申请日：2007-03-13

Applicant: INTEL CORP

Inventor： MOZAK CHRISTOPHER ,  GILBERT JEFFREY ,  SRINIVASA GANAPATI

IPC: G06F13/12 ,  G06F13/10 ,  G06F13/20

Abstract: In one embodiment, the present invention includes a processor having multiple processor cores to execute instructions, with each of the cores including dedicated digital interface circuitry. The processor further includes an analog interface coupled to the cores via the digital interface circuitry. The analog interface may be used to communicate traffic between a package including the cores and an interconnect such as a shared bus coupled thereto. Other embodiments are described and claimed.