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    ACCELERATOR FOR SPARSE-DENSE MATRIX MULTIPLICATION
    2.
    发明专利
    ACCELERATOR FOR SPARSE-DENSE MATRIX MULTIPLICATION 未知

    公开(公告)号：FI3779681T3

    公开(公告)日：2024-06-28

    申请号：FI20199012

    申请日：2019-02-13

    Applicant: INTEL CORP

    Inventor： NARAYANAMOORTHY SRINIVASAN ,  SATISH NADATHUR RAJAGOPALAN ,  SUPRUN ALEXEY ,  JANIK KENNETH J

    IPC: G06F9/30

    Abstract: Disclosed embodiments relate to multiply-accumulate operations. In one example, a processor comprises: a cache to store data; at least one core coupled to the cache. The at least one core comprises: execution circuitry to perform multiply-accumulate operations with a first source matrix and a second source matrix to generate a result matrix responsive to an instruction, wherein the first source matrix is a sparse matrix having non-zero data elements located at certain positions, wherein the first source matrix is stored in a compressed format that identifies the positions of the non-zero data elements in the first source matrix. The execution circuitry further comprises: a plurality of multiply-accumulate circuits to perform a plurality of multiply-add operations to multiply the non-zero data elements of the first source matrix by corresponding data elements of the second source matrix identified based on the positions in the compressed format to generate a plurality of products, and to add the plurality of products to accumulated values to generate data elements of the result matrix.

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