公开(公告)号：EP3123473A4

公开(公告)日：2017-11-29

申请号：EP15768870

申请日：2015-03-03

Applicant: INTEL CORP

Inventor： KULKARNI JAYDEEP P ,  THAPLOO ANUPAMA ,  RAJWANI IQBAL ,  KOO KYUNG-HOAE ,  KARL ERIC A ,  KHELLAH MUHAMMAD

IPC: G11C7/10 ,  G11C7/06 ,  G11C7/12 ,  G11C8/08 ,  G11C11/419

CPC classification number: G11C7/12 ,  G11C7/1048 ,  G11C7/1069 ,  G11C7/22 ,  G11C11/419 ,  G11C17/16 ,  G11C2207/005

Abstract: Embodiments include apparatuses, methods, and systems related to an assist circuit that may be coupled to one or more components of a memory system to selectively lower a supply voltage that is delivered to the component. For example, the assist circuit may be coupled to a plurality of bitcells (e.g., register file bitcells). The assist circuit may selectively lower the supply voltage delivered to the bitcells during at least a portion of a write operation and/or during an inactive state of the bitcells. Additionally, or alternatively, the assist circuit may be coupled to a read circuit to selectively lower the supply voltage delivered to the read circuit during an inactive state of the read circuit. The assist circuit may include a control transistor coupled in parallel with one or more diodes between a main supply rail and a supply node of the bitcells and/or read circuit.