公开(公告)号：WO1996012295A1

公开(公告)日：1996-04-25

申请号：PCT/US1995009529

申请日：1995-07-14

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  MYERS, Alan, M. ,  CHARVAT, Peter, K. ,  LETSON, Thomas, A. ,  YANG, Shi-ning ,  BAI, Peng

IPC: H01L21/302

CPC classification number: H01L21/76805 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/76838 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S257/915 ,  H01L2924/00

Abstract: A novel high performance and reliable interconnection structure for preventing via delamination. The interconnection structure of the present invention comprises a via connection (212) which extends into and undercuts an underlying interconnection line (202) to lock the via connection (212) into the interconnection line (202).

Abstract translation: 一种新颖的高性能和可靠的互连结构，用于防止通过分层。 本发明的互连结构包括一个通孔连接（212），该通孔连接（212）延伸到下面的互连线（202）并将其下切以将通孔连接（212）锁定到互连线（202）中。

公开(公告)号：WO2016209242A1

公开(公告)日：2016-12-29

申请号：PCT/US2015/037762

申请日：2015-06-25

Applicant: INTEL CORPORATION

Inventor： TONG, Xiaoghong ,  HAFEZ, Walid M. ,  MA, Zhiyong ,  BAI, Peng ,  JAN, Chia-Hong ,  CHEN, Zhanping

IPC: H01L23/62

CPC classification number: H01L27/11206 ,  G11C17/16 ,  H01L23/5252

Abstract: The controlled modification of an antifuse programming voltage is described. In one example, an antifuse circuit is formed on a substrate, including a gate area of the antifuse circuit. A molecule is implanted into the gate area to damage the structure of the gate area. Electrodes are formed over the gate areas to connect the antifuse circuit to other components.

Abstract translation: 描述了反熔丝编程电压的可控修改。 在一个示例中，在包括反熔丝电路的栅极区域的基板上形成反熔丝电路。 将一个分子注入到栅极区域以损坏栅极区域的结构。 电极形成在栅极区域上，以将反熔丝电路连接到其他部件。

公开(公告)号：EP4177937A1

公开(公告)日：2023-05-10

申请号：EP22200107.5

申请日：2022-10-06

Applicant: INTEL Corporation

Inventor： BAI, Peng ,  JEONG, James Y. ,  JAN, Chia-Hong ,  LEIB, Jeffrey S. ,  PLEKHANOV, Pavel S. ,  BASU, Debashish ,  AN, Seungdo ,  O'BRIEN, Daniel B.

IPC: H01L21/768

Abstract: Integrated circuit interconnect structure compatible with single damascene techniques and that includes a non-copper via comprising metal(s) of low resistivity that can be deposited at low temperature in a manner that also ensures good adhesion. Metal(s) suitable for the non-copper via may have BCC crystallinity that can advantageously template favorable crystallinity within a diffusion barrier of the upper-level interconnect feature, further reducing electrical resistance of an interconnect structure.

公开(公告)号：EP3314647A1

公开(公告)日：2018-05-02

申请号：EP15896529.3

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： TONG, Xiaoghong ,  HAFEZ, Walid M. ,  MA, Zhiyong ,  BAI, Peng ,  JAN, Chia-Hong ,  CHEN, Zhanping

IPC: H01L23/62

CPC classification number: H01L27/11206 ,  G11C17/16 ,  H01L23/5252

Abstract: The controlled modification of an antifuse programming voltage is described. In one example, an antifuse circuit is formed on a substrate, including a gate area of the antifuse circuit. A molecule is implanted into the gate area to damage the structure of the gate area. Electrodes are formed over the gate areas to connect the antifuse circuit to other components.

公开(公告)号：EP1008175A1

公开(公告)日：2000-06-14

申请号：EP96933088.5

申请日：1996-09-23

Applicant: INTEL CORPORATION

Inventor： BAI, Peng ,  CADIEN, Kenneth, C. ,  CHENG, Lie-Yea ,  PRINCE, Matthew, J.

IPC: H01L21/44

CPC classification number: H01L21/76801 ,  H01L21/76828

Abstract: A method of forming a novel high density interconnection structure. According to the present invention, first an insulating layer (206) is formed over a semiconductor substrate. The first insulating layer is then planarized. Next, a second insulating layer (212) is formed above the first planarized insulating layer. An opening is then etched through the first and second insulating layers. A conductive material (226) is then deposited into the opening and onto the top surface of the second insulating layer. Next, the conductive material is polished back from the second insulating layer so as to form a conductively filled opening which is substantially planar with the second insulating layer.

公开(公告)号：EP0852809A1

公开(公告)日：1998-07-15

申请号：EP96933891.0

申请日：1996-09-25

Applicant: INTEL CORPORATION

Inventor： RASTOGI, Rajiv ,  BAI, Peng ,  AHMED, Sohail ,  MEYER, William, K.

IPC: H01L21 ,  H01L23

CPC classification number: H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metal stack (35) for use in an integrated circuit demonstrating improved electromigration properties. A base layer (31) of approximately 185Å of titanium is formed on an ILD followed by the formation of the bulk conductor layer (32) such as an aluminum-copper alloy layer. A capping layer (33) of approximately 185Å of titanium is formed on the bulk conductor layer (32). Finally, an antireflective coating (ARC) (34) of titanium nitride is formed on the capping layer (33).