公开(公告)号：US12278289B2

公开(公告)日：2025-04-15

申请号：US18414290

申请日：2024-01-16

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Carl Naylor ,  Chelsey Dorow ,  Kirby Maxey ,  Tanay Gosavi ,  Ashish Verma Penumatcha ,  Shriram Shivaraman ,  Chia-Ching Lin ,  Sudarat Lee ,  Uygar E. Avci

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02

Abstract: Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.

公开(公告)号：US20250113540A1

公开(公告)日：2025-04-03

申请号：US18375055

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Carl H. Naylor ,  Rachel Steinhardt ,  Mahmut Sami Kavrik ,  Chia-Ching Lin ,  Andrey Vyatskikh ,  Kevin O’Brien ,  Kirby Maxey ,  Ashish Verma Penumatcha ,  Uygar Avci ,  Matthew Metz ,  Chelsey Dorow

IPC: H01L29/49 ,  H01L21/02 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/76 ,  H01L29/775 ,  H01L29/786

Abstract: Techniques and mechanisms for providing gate dielectric structures of a transistor. In an embodiment, the transistor comprises a thin channel structure which comprises one or more layers of a transition metal dichalcogenide (TMD) material. The channel structure forms two surfaces on opposite respective sides thereof, wherein the surfaces extend to each of two opposing edges of the channel structure. A composite gate dielectric structure comprises first bodies of a first dielectric material, wherein the first bodies each adjoin a different respective one of the two opposing edges, and variously extend to each of the surfaces two surfaces. The composite gate dielectric structure further comprises another body of a second dielectric material other than the first dielectric material. In another embodiment, the other body adjoins one or both of the two surfaces, and extends along one or both of the two surfaces to each of the first bodies.

公开(公告)号：US12266720B2

公开(公告)日：2025-04-01

申请号：US17129486

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Chelsey Dorow ,  Kevin O'Brien ,  Sudarat Lee ,  Kirby Maxey ,  Ashish Verma Penumatcha ,  Tanay Gosavi ,  Patrick Theofanis ,  Chia-Ching Lin ,  Uygar Avci ,  Matthew Metz ,  Shriram Shivaraman

IPC: H01L29/76 ,  H01L21/02 ,  H01L21/8256 ,  H01L27/092 ,  H01L29/24

Abstract: Transistor structures with monocrystalline metal chalcogenide channel materials are formed from a plurality of template regions patterned over a substrate. A crystal of metal chalcogenide may be preferentially grown from a template region and the metal chalcogenide crystals then patterned into the channel region of a transistor. The template regions may be formed by nanometer-dimensioned patterning of a metal precursor, a growth promoter, a growth inhibitor, or a defected region. A metal precursor may be a metal oxide suitable, which is chalcogenated when exposed to a chalcogen precursor at elevated temperature, for example in a chemical vapor deposition process.

公开(公告)号：US20240222485A1

公开(公告)日：2024-07-04

申请号：US18091209

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Mahmut Sami Kavrik ,  Tristan Tronic ,  Chelsey Dorow ,  Kevin O?Brien ,  Uygar Avci ,  Carl H. Naylor ,  Chia-Ching Lin ,  Dominique Adams ,  Matthew Metz ,  Ande Kitamura ,  Scott B. Clendenning

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/06 ,  H01L29/26 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/26 ,  H01L29/42392 ,  H01L29/66969

Abstract: A transistor structure includes a stack of nanoribbons coupling source and drain terminals. The nanoribbons may each include a pair of crystalline interface layers and a channel layer between the interface layers. The channel layers may be a molecular monolayer, including a metal and a chalcogen, with a thickness of less than 1 nm. The channel layers may be substantially monocrystalline, and the interface layers may be lattice matched to the channel layers. The channel layers may be epitaxially grown over the lattice-matched interface layers. The crystalline interface layers may be grown over sacrificial layers when forming the stack of nanoribbons.

公开(公告)号：US20220199783A1

公开(公告)日：2022-06-23

申请号：US17133087

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Ashish Verma Penumatcha ,  Kevin O'Brien ,  Chelsey Dorow ,  Kirby Maxey ,  Carl Naylor ,  Tanay Gosavi ,  Sudarat Lee ,  Chia-Ching Lin ,  Seung Hoon Sung ,  Uygar Avci

IPC: H01L29/24 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L27/22 ,  H01L27/24

Abstract: A transistor includes a first channel layer over a second channel layer, where the first and the second channel layers include a monocrystalline transition metal dichalcogenide (TMD). The transistor structure further includes a source structure coupled to a first end of the first and second channel layers, a drain structure coupled to a second end of the first and second channel layers, a gate structure between the source material and the drain material, and between the first channel layer and the second channel layer. The transistor further includes a spacer laterally between the gate structure and the and the source structure and between the gate structure and the drain structure. A liner is between the spacer and the gate structure. The liner is in contact with the first channel layer and the second channel layer and extends between the gate structure and the respective source structure and the drain structure.

公开(公告)号：US20250113599A1

公开(公告)日：2025-04-03

申请号：US18477414

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Rachel A. Steinhardt ,  Kevin P. O'Brien ,  Ashish Verma Penumatcha ,  Carl Hugo Naylor ,  Kirby Maxey ,  Pratyush P. Buragohain ,  Chelsey Dorow ,  Mahmut Sami Kavrik ,  Wouter Mortelmans ,  Marko Radosavljevic ,  Uygar E. Avci ,  Matthew V. Metz

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/26 ,  H01L29/66 ,  H01L29/775

Abstract: Methods for doping 2D transistor devices and resulting architectures. The use and placement of oxide dopants, such as, but not limited to, GeOx, enable control over threshold voltage performance and contact resistance of 2D transistor devices. Architectures include distinct stoichiometry compositions.

公开(公告)号：US12176388B2

公开(公告)日：2024-12-24

申请号：US16914137

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Kevin O'Brien ,  Chelsey Dorow ,  Kirby Maxey ,  Carl Naylor ,  Shriram Shivaraman ,  Sudarat Lee ,  Tanay Gosavi ,  Chia-Ching Lin ,  Uygar Avci ,  Ashish Verma Penumatcha

IPC: H01L29/04 ,  H01L21/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/20 ,  H01L29/267

Abstract: A transistor structure includes a first channel layer over a second channel layer, where the first and the second channel layers include a monocrystalline transition metal dichalcogenide (TMD). The transistor structure further includes a source material coupled to a first end of the first and second channel layers, a drain material coupled to a second end of the first and second channel layers, a gate electrode between the source material and the drain material, and between the first channel layer and the second channel layer and a gate dielectric between the gate electrode and each of the first channel layer and the second channel layer.

公开(公告)号：US20240222428A1

公开(公告)日：2024-07-04

申请号：US18091206

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Chelsey Dorow ,  Carl H. Naylor ,  Kirby Maxey ,  Kevin O'Brien ,  Ashish Verma Penumatcha ,  Chia-Ching Lin ,  Uygar Avci ,  Matthew Metz ,  Sudarat Lee ,  Ande Kitamura ,  Scott B. Clendenning ,  Mahmut Sami Kavrik

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/04 ,  H01L29/08 ,  H01L29/22 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823412 ,  H01L27/0886 ,  H01L29/04 ,  H01L29/0847 ,  H01L29/22 ,  H01L29/778 ,  H01L29/78696

Abstract: A transistor has multiple channel regions coupling source and drain structures, and a seed material is between one of the source or drain structures and a channel material, which includes a metal and a chalcogen. Each channel region may include a nanoribbon. A nanoribbon may have a monocrystalline structure and a thickness of a monolayer, less than 1 nm. A nanoribbon may be free of internal grain boundaries. A nanoribbon may have an internal grain boundary adjacent an end opposite the seed material. The seed material may directly contact the first of the source or drain structures, and the channel material may directly contact the second of the source or drain structures.

公开(公告)号：US20230420364A1

公开(公告)日：2023-12-28

申请号：US17849207

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Tristan A. Tronic ,  Ande Kitamura ,  Ashish Verma Penumatcha ,  Carl Hugo Naylor ,  Chelsey Dorow ,  Kirby Maxey ,  Scott B. Clendenning ,  Sudarat Lee ,  Uygar E. Avci

IPC: H01L23/528 ,  H01L23/522 ,  H01L29/423 ,  H01L29/18 ,  H01L27/092 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L29/42392 ,  H01L29/18 ,  H01L27/0924 ,  H01L29/78696 ,  H01L29/66742

Abstract: A microelectronic device, a semiconductor package including the device, an IC device assembly including the package, and a method of making the device. The device includes a substrate; a first structure on the substrate, the first structure corresponding to a front end of line (FEOL) stack of the device and including a plurality of first transistors therein; and a second structure on the substrate, the second structure corresponding to a back end of line (BEOL) stack of the device, and including a plurality of second transistors therein, the plurality of second transistors including a transition metal dichalcogenide (TMD) material. The second transistors are part of a voltage regulation architecture to regulate voltage supply to the die.

公开(公告)号：US20230099814A1

公开(公告)日：2023-03-30

申请号：US17485160

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Kirby Maxey ,  Ashish Verma Penumatcha ,  Carl Naylor ,  Chelsey Dorow ,  Kevin O'Brien ,  Shriram Shivaraman ,  Tanay Gosavi ,  Uygar Avci

IPC: H01L29/76 ,  H01L29/24 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/443 ,  H01L29/66

Abstract: Transistors, devices, systems, and methods are discussed related to transistors including 2D material channels and heterogeneous 2D materials on the 2D material channels and coupled to source and drain metals, and their fabrication. The 2D material channels of the transistor allow for gate length scaling, improved switching performance, and other advantages and the heterogeneous 2D materials improve contact resistance of the transistor devices.