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1.
公开(公告)号:US20230421040A1
公开(公告)日:2023-12-28
申请号:US17851997
申请日:2022-06-28
Applicant: Intel Corporation
Inventor: Tamir Salus , Shunjiang Xu , Christopher Schaef
CPC classification number: H02M1/0043 , H02M1/088 , H02M3/155 , H02M1/0012
Abstract: Techniques and mechanisms for facilitating a scalable delivery of current to an inductor of a voltage regulator. In an embodiment, a hardware interface of integrated circuit (IC) die accommodates coupling of the IC die to multiple inductors. The hardware interface comprises contacts which are each to couple the IC die to a respective one of the multiple inductors. A phase circuit of the IC die includes multiple cells which are each coupled to a different respective contact of a plurality of contacts of the hardware interface. A digital controller of the IC die is operable to select any of various combinations of the multiple cells each to conduct a respective current with a corresponding one of the plurality of contacts. In another embodiment, the plurality of contacts are arranged as a multi-row, multi-column array.
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2.
公开(公告)号:US10897364B2
公开(公告)日:2021-01-19
申请号:US15846045
申请日:2017-12-18
Applicant: Intel Corporation
Inventor: Vivek De , Krishnan Ravichandran , Harish Krishnamurthy , Khondker Ahmed , Sriram Vangal , Vaibhav Vaidya , Turbo Majumder , Christopher Schaef , Suhwan Kim , Xiaosen Liu , Nachiket Desai
IPC: H04L9/32
Abstract: Spin Hall Effect (SHE) magneto junction memory cells (e.g., magnetic tunneling junction (MTJ) or spin valve based memory cells) are used to implement high entropy physically unclonable function (PUF) arrays utilizing stochastics interactions of both parameter variations of the SHE-MTJ structures as well as random thermal noises. An apparatus is provided which comprises: an array of PUF devices, wherein an individual device of the array comprises a magnetic junction and an interconnect, wherein the interconnect comprises a spin orbit coupling material; a circuitry to sense values stored in the array, and to provide an output; and a comparator to compare the output with a code.
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公开(公告)号:US20170187187A1
公开(公告)日:2017-06-29
申请号:US14998328
申请日:2015-12-23
Applicant: Intel Corporation
Inventor: Sally Amin , Sergio Carlo , Harish Krishnamurthy , Christopher Schaef , Vaibhav Vaidya
Abstract: A power regulator includes a plurality of harvester switches, each coupled to receive a separate energy source, a plurality of load switches, each coupled to supply power to a separate load, an inductor to store energy received from one or more energy sources and release the energy to supply the power to one or more loads and a controller to control charging of the inductor via activation of one or more of the harvester switches and discharging of the inductor via activation of one or more of the load switches.
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公开(公告)号:US20240297586A1
公开(公告)日:2024-09-05
申请号:US18177426
申请日:2023-03-02
Applicant: Intel Corporation
Inventor: Keng Chen , Shunjiang Xu , Christopher Schaef , Tamir Salus , Kishan Joshi , Arvind Raghavan , Huanhuan Zhang
CPC classification number: H02M3/1584 , G06F1/26
Abstract: Embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to multiphase power converters and how current level outputs of each phase circuit are calibrated. The multiple phase circuits are grouped into multiple subsets, wherein one phase circuit of each subset is designated as a reference phase circuit. The reference phase circuits of each subset are calibrated together, using, for example, a closed loop daisy chain technique where each reference phase circuit calibrates their current output to the current output of the previous phase circuit, or alternatively, a current averaging technique where each reference phase circuit balances their current output to the average output of the reference phase circuits. The other phase circuits in each subset calibrate their current level outputs to the reference phase circuits in their subset using, for example, an open loop daisy chain technique, a reference/follower technique or by calibrating their output to the average output of the reference phase circuits.
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公开(公告)号:US20230068300A1
公开(公告)日:2023-03-02
申请号:US17412724
申请日:2021-08-26
Applicant: INTEL CORPORATION
Inventor: Krishna Bharath , William J. Lambert , Christopher Schaef , Alexander Lyakhov , Kaladhar Radhakrishnan , Sriram Srinivasan
Abstract: A microelectronic assembly is provided, comprising a first IC die having an electrical load circuit, a second IC die having a portion of a voltage regulator (VR) electrically coupled to the first IC die, a package substrate having inductors of the VR electrically coupled to the first IC die and the second IC die, and a mold compound between the first IC die and the package substrate. The VR receives power at a first voltage from the package substrate and provides power at a second voltage to the electrical load circuit, the second voltage being lower than the first voltage. In various embodiments, the second IC die is in the mold compound. In some embodiments, the mold compound and the second IC die are comprised in a discrete interposer electrically coupled to the first IC die with die-to-die interconnects and to the package substrate with die-to-package substrate interconnects.
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公开(公告)号:US11411491B2
公开(公告)日:2022-08-09
申请号:US16642853
申请日:2017-09-29
Applicant: Intel Corporation
Inventor: Vivek De , Krishnan Ravichandran , Harish Krishnamurthy , Khondker Ahmed , Sriram Vangal , Vaibhav Vaidya , Turbo Majumder , Christopher Schaef , Suhwan Kim , Xiaosen Liu , Nachiket Desai
Abstract: Voltage dividing circuitry is provided for use in a voltage converter for converting at least one input Direct Current, DC voltage to a plurality of output DC voltages. The voltage dividing circuitry including a voltage input port to receive an input DC voltage and an inductor having an input-side switch node and an output-side switch node. The output side switch node is connectable to one of a plurality of voltage output ports to supply a converted value of the input DC voltage as an output DC voltage. The flying capacitor interface has a plurality of switching elements and at least one flying capacitor, the flying capacitor interface to divide the input DC voltage to provide a predetermined fixed ratio of the input DC voltage at the input-side switch node of the inductor. A voltage converter and a power management integrated circuit having the voltage dividing circuitry are also provided.
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公开(公告)号:US20190199206A1
公开(公告)日:2019-06-27
申请号:US15855683
申请日:2017-12-27
Applicant: INTEL CORPORATION
Inventor: Christopher Schaef , Vaibhav Vaidya , Suhwan Kim
Abstract: In some examples, an apparatus for reference voltage generation includes a plurality of reference voltage rails each with a corresponding reference voltage, a first controller, and a second controller. The first controller is to cycle through the plurality of reference voltage rails and maintain the reference voltages in a synchronous mode. The second controller is to detect an event and provide an indication to the first controller to update in an asynchronous mode one of the plurality of reference voltages in response to the event. The first controller is to update in an asynchronous mode the one of the plurality of reference voltages in response to the event.
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8.
公开(公告)号:US20190190725A1
公开(公告)日:2019-06-20
申请号:US15846045
申请日:2017-12-18
Applicant: Intel Corporation
Inventor: Vivek De , Krishnan Ravichandran , Harish Krishnamurthy , Khondker Ahmed , Sriram Vangal , Vaibhav Vaidya , Turbo Majumder , Christopher Schaef , Suhwan Kim , Xiaosen Liu , Nachiket Desai
IPC: H04L9/32
CPC classification number: H04L9/3278
Abstract: An apparatus is provided which comprises: an array of physically unclonable function (PUF) devices, wherein an individual device of the array comprises a magnetic junction and an interconnect, wherein the interconnect comprises a spin orbit coupling material; a circuitry to sense values stored in the array, and to provide an output; and a comparator to compare the output with a code.
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公开(公告)号:US20190103824A1
公开(公告)日:2019-04-04
申请号:US15721548
申请日:2017-09-29
Applicant: Intel Corporation
Inventor: Suhwan Kim , Vaibhav Vaidya , Christopher Schaef
Abstract: An embodiment of a harvester apparatus comprising two or more charge pump stages may include at least a first charge pump stage to receive an alternating current source, and a second charge pump stage coupled to the first charge pump stage.
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10.
公开(公告)号:US20190094931A1
公开(公告)日:2019-03-28
申请号:US15718991
申请日:2017-09-28
Applicant: INTEL CORPORATION
Inventor: Khondker Z. Ahmed , Vivek K. De , Nachiket V. Desai , Suhwan Kim , Harish K. Krishnamurthy , Xiaosen Liu , Turbo Majumder , Krishnan Ravichandran , Christopher Schaef , Vaibhav Vaidya , Sriram R. Vangal
Abstract: Various embodiments of the invention may analyze previous patterns of harvested energy to predict future patterns of available harvested energy. This prediction may then be used to choose from among multiple methods of energy reduction techniques. The energy reduction techniques may include multiple versions of reducing or modifying instruction execution. Reduced instruction execution may include reducing the precision of various calculations.
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