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    METHOD AND APPARATUS FOR PARTIAL CACHE LINE SPARING
    2.
    发明申请
    METHOD AND APPARATUS FOR PARTIAL CACHE LINE SPARING 审中-公开
    部分高速缓存行配置的方法和设备

    公开(公告)号：WO2017112269A1

    公开(公告)日：2017-06-29

    申请号：PCT/US2016/063425

    申请日：2016-11-22

    Applicant: INTEL CORPORATION

    Inventor： DAS, Debaleena ,  AGARWAL, Rajat ,  MORRIS, Brian S.

    IPC: G06F11/07

    CPC classification number: G06F11/0793 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/1064

    Abstract: Provided are an apparatus and method to store data from a cache line at locations having errors in a sparing directory. In response to a write operation having write data for locations in one of the cache lines, the write data for a location in the cache line having an error is written to an entry in a sparing directory including an address of the cache line.

    Abstract translation: 提供了一种装置和方法，用于将来自高速缓存行的数据存储在备用目录中存在错误的位置处。 响应于具有用于一个高速缓存行中的位置的写入数据的写入操作，用于具有错误的高速缓存行中的位置的写入数据被写入包括高速缓存行的地址的备用目录中的条目。 p>

    DYNAMIC APPLICATION OF ECC BASED ON ERROR TYPE
    3.
    发明申请
    DYNAMIC APPLICATION OF ECC BASED ON ERROR TYPE 审中-公开
    基于错误类型的ECC的动态应用

    公开(公告)号：WO2016160275A1

    公开(公告)日：2016-10-06

    申请号：PCT/US2016/021146

    申请日：2016-03-07

    Applicant: INTEL CORPORATION

    Inventor： DAS, Debaleena ,  AGARWAL, Rajat

    IPC: G06F11/10 ,  G06F11/16

    CPC classification number: G11C29/42 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1048 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/0411

    Abstract: Error correction in a memory subsystem includes determining whether an error is a transient error or a persistent error, and adjusting an approach to ECC (error checking and correction) based on error type. The type of error can be determined by a built in self-test. If the error is a persistent error, the memory controller can perform in erasure mode, including correcting an erasure for an identified error location prior to applying an ECC correction algorithm. Otherwise, if the error is transient, the memory controller can perform standard full ECC correction by applying the ECC correction algorithm.

    Abstract translation: 存储器子系统中的错误校正包括确定错误是否是瞬态错误或持续错误，以及基于错误类型调整ECC（错误检查和校正）的方法。 错误的类型可以通过内置的自检来确定。 如果错误是持续错误，则存储器控制器可以在擦除模式下执行，包括在应用ECC校正算法之前校正对所识别的错误位置的擦除。 否则，如果错误是瞬态的，则存储器控制器可以通过应用ECC校正算法执行标准的全ECC校正。

    EXTRACTING SELECTIVE INFORMATION FROM ON-DIE DRAM ECC
    5.
    发明申请
    EXTRACTING SELECTIVE INFORMATION FROM ON-DIE DRAM ECC 审中-公开
    从芯片DRAM ECC提取选择信息

    公开(公告)号：WO2016160274A1

    公开(公告)日：2016-10-06

    申请号：PCT/US2016/021142

    申请日：2016-03-07

    Applicant: INTEL CORPORATION

    Inventor： DAS, Debaleena ,  NALE, Bill ,  BANES, Kuljit S ,  HALBERT, John B

    IPC: G06F11/10

    CPC classification number: G06F11/1048 ,  G06F11/00 ,  G06F11/1008 ,  G06F11/1076 ,  G06F11/1084

    Abstract: Error correction in a memory subsystem includes a memory device generating internal check bits after performing internal error detection and correction, and providing the internal check bits to the memory controller. The memory device performs internal error detection to detect errors in read data in response to a read request from the memory controller. The memory device selectively performs internal error correction if an error is detected in the read data. The memory device generates check bits indicating an error vector for the read data after performing internal error detection and correction, and provides the check bits with the read data to the memory controller in response to the read request. The memory controller can apply the check bits for error correction external to the memory device.

    Abstract translation: 存储器子系统中的错误校正包括在执行内部错误检测和校正之后产生内部校验位的存储器件，以及向内存控制器提供内部校验位。 存储器件执行内部错误检测以响应于来自存储器控制器的读取请求来检测读取数据中的错误。 如果在读取的数据中检测到错误，则存储器件选择性地执行内部纠错。 在执行内部错误检测和校正之后，存储器件产生指示读取数据的错误向量的校验位，并且响应于读取请求将校验位与读取的数据提供给存储器控制器。 存储器控制器可以将校验位应用于存储器件外部的纠错。

    ENHANCED STORAGE OF METADATA UTILIZING IMPROVED ERROR DETECTION AND CORRECTION IN COMPUTER MEMORY
    6.
    发明申请
    ENHANCED STORAGE OF METADATA UTILIZING IMPROVED ERROR DETECTION AND CORRECTION IN COMPUTER MEMORY 审中-公开
    使用计算机内存中改进的错误检测和校正的元数据的增强存储

    公开(公告)号：WO2013147794A1

    公开(公告)日：2013-10-03

    申请号：PCT/US2012/031216

    申请日：2012-03-29

    Applicant: INTEL CORPORATION ,  DAS, Debaleena ,  AGARWAL, Rajat ,  HUDDLESTON, C. Scott

    Inventor： DAS, Debaleena ,  AGARWAL, Rajat ,  HUDDLESTON, C. Scott

    IPC: G06F11/10 ,  G06F12/16

    CPC classification number: G06F11/1666 ,  G06F11/1064

    Abstract: A novel ECC scheme is disclosed that offers an error protection level that is at least the same as (if not better than) that of the conventional ECC scheme without negatively impacting latency and design complexity. Embodiments of the present disclosure utilize an ECC scheme which leaves up to extra 2B for metadata storage by changing the error detection and correction process flow. The scheme adopts an early error detection mechanism, and tailors the need for subsequent error correction based on the results of the early detection.

    Abstract translation: 公开了一种新颖的ECC方案，其提供至少与常规ECC方案的错误保护级别相同（如果不是更好），而不会对延迟和设计复杂性产生负面影响。 本公开的实施例利用ECC方案，其通过改变错误检测和校正处理流程而留下额外的2B用于元数据存储。 该方案采用早期错误检测机制，根据早期检测结果调整后续纠错的需要。

    DYNAMICALLY CHANGING LOCKSTEP CONFIGURATION
    7.
    发明申请
    DYNAMICALLY CHANGING LOCKSTEP CONFIGURATION 审中-公开
    动态更改LOCKSTEP配置

    公开(公告)号：WO2016127143A1

    公开(公告)日：2016-08-11

    申请号：PCT/US2016/016905

    申请日：2016-02-06

    Applicant: INTEL CORPORATION

    Inventor： DAS, Debaleena ,  HUANG, George H ,  LING, Jing ,  DAFTARI, Reza E ,  GANESAN, Meera

    IPC: G06F11/16

    CPC classification number: G06F11/1662 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/0647 ,  G06F3/0683 ,  G06F11/00 ,  G06F11/2094 ,  G06F2201/825

    Abstract: Memory subsystem error management enables dynamically changing lockstep partnerships. A memory subsystem has a lockstep partnership relationship between a first memory portion and a second memory portion to spread error correction over the pair of memory resources. The lockstep partnership can be preconfigured. In response to detecting a hard error in the lockstep partnership, the memory subsystem can cancel or reverse the lockstep partnership between the first memory portion and the second memory portion and create or set a new lockstep partnership. The detected error can be a second hard error in the lockstep partnership. The memory subsystem can create new lockstep partnerships between the first memory portion and a third memory portion as lockstep partners and between the second memory portion and a fourth memory portion as lockstep partners. The memory subsystem can also be configured to change the granularity of the lockstep partnership when changing partnerships.

    Abstract translation: 内存子系统错误管理可实现动态更改的锁步合作伙伴关系。 存储器子系统具有在第一存储器部分和第二存储器部分之间的锁步合作关系，以在所述一对存储器资源上扩展纠错。 锁定合作伙伴关系可以预先配置。 响应于检测锁步伙伴关系中的硬错误，存储器子系统可以取消或反转第一存储器部分和第二存储器部分之间的锁步合作关系，并创建或设置新的锁步伙伴关系。 检测到的错误可能是锁步伙伴关系中的第二个硬错误。 存储器子系统可以在第一存储器部分和第三存储器部分之间创建新的锁步合作关系，作为锁步伙伴，并且在第二存储器部分和作为锁步伙伴的第四存储器部分之间。 内存子系统也可以配置为在更改合作伙伴关系时更改锁步伙伴关系的粒度。

    METHOD AND APPARATUS FOR REVERSE MEMORY SPARING
    8.
    发明申请
    METHOD AND APPARATUS FOR REVERSE MEMORY SPARING 审中-公开
    反向记忆体的方法和装置

    公开(公告)号：WO2016048673A1

    公开(公告)日：2016-03-31

    申请号：PCT/US2015/049351

    申请日：2015-09-10

    Applicant: INTEL CORPORATION

    Inventor： HUANG, George, H. ,  DAS, Debaleena ,  MORRIS, Brian, S. ,  AGARWAL, Rajat

    IPC: G06F11/16 ,  G06F11/07 ,  G06F12/00

    CPC classification number: G11C29/883 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/0793 ,  G06F11/1666 ,  G06F11/2094

    Abstract: An apparatus and method are described for performing forward and reverse memory sparing operations. For example, one embodiment of a processor comprises memory sparing logic to perform a first forward memory sparing operation at a first level of granularity in response to detecting a memory failure; the memory sparing logic to perform a reverse memory sparing operation in response to a determination of an improved sparing state having a second level of granularity; and the memory sparing logic to responsively perform a second forward memory sparing operation at the second level of granularity.

    Abstract translation: 描述了用于执行前向和反向存储器备用操作的装置和方法。 例如，处理器的一个实施例包括存储器备用逻辑，以响应于检测到存储器故障以第一粒度级执行第一前向存储器备用操作; 所述存储器备用逻辑用于响应于确定具有第二粒度级别的改进的备用状态来执行反向存储器备用操作; 并且所述存储器备用逻辑以所述第二粒度级响应地执行第二转发存储器备用操作。

    DYNAMICALLY CHANGING LOCKSTEP CONFIGURATION
    10.
    发明公开
    DYNAMICALLY CHANGING LOCKSTEP CONFIGURATION 审中-公开
    动态改变锁定配置

    公开(公告)号：EP3254198A1

    公开(公告)日：2017-12-13

    申请号：EP16747397.4

    申请日：2016-02-06

    Applicant: Intel Corporation

    Inventor： DAS, Debaleena ,  HUANG, George H ,  LING, Jing ,  DAFTARI, Reza E ,  GANESAN, Meera

    IPC: G06F11/16

    CPC classification number: G06F11/1662 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/0647 ,  G06F3/0683 ,  G06F11/00 ,  G06F11/2094 ,  G06F2201/825

    Abstract: Memory subsystem error management enables dynamically changing lockstep partnerships. A memory subsystem has a lockstep partnership relationship between a first memory portion and a second memory portion to spread error correction over the pair of memory resources. The lockstep partnership can be preconfigured. In response to detecting a hard error in the lockstep partnership, the memory subsystem can cancel or reverse the lockstep partnership between the first memory portion and the second memory portion and create or set a new lockstep partnership. The detected error can be a second hard error in the lockstep partnership. The memory subsystem can create new lockstep partnerships between the first memory portion and a third memory portion as lockstep partners and between the second memory portion and a fourth memory portion as lockstep partners. The memory subsystem can also be configured to change the granularity of the lockstep partnership when changing partnerships.

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