公开(公告)号：WO2003085932A1

公开(公告)日：2003-10-16

申请号：PCT/US2003/009626

申请日：2003-03-28

Applicant: INTEL CORPORATION

Inventor： HUANG, Anguo ,  LING, Jing ,  CAIA, Jean-Michel ,  CALDERON, Juan-Carlos ,  JOSHI, Vivek

IPC: H04L29/06

CPC classification number: H04L47/6215 ,  H04L47/10 ,  H04L47/39 ,  H04L47/50 ,  H04L47/521 ,  H04L47/627

Abstract: The rate-based scheduling for a network application is used to control the bandwidth available to a flow while scheduling the transmission of the flow. The rate-based scheduling uses rate credits to represent the amount of data a flow is permitted to transmit and only permits a flow to transmit if the flow has a rate credit available. A flow is permitted to transmit only if the peak packet rate for the scheduler has not been exceeded.

Abstract translation: 用于网络应用的基于速率的调度用于在调度流的传输的同时控制流可用的带宽。 基于速率的调度使用速率信用来表示流被允许传输的数据量，并且仅当流具有可用的费率信用时才允许流传输。 只有当没有超过调度程序的峰值分组速率时，才允许流量传输。

公开(公告)号：WO2003102725A3

公开(公告)日：2003-12-11

申请号：PCT/US2003/014874

申请日：2003-05-08

Applicant: INTEL CORPORATION

Inventor： CALDERON, Juan-Carlos ,  LING, Jing ,  CAIA, Jean-Michel ,  JOSHI, Vivek ,  HUANG, Anguo

IPC: H04L12/56

Abstract: Memory access efficiency for packet applications may be improved by transferring full partitions of data. The number of full partitions written to external memory may be increased by temporarily storing packets using on-chip memory that is on a chip with the processor. Before writing packets to external memory, packets of length smaller than the external memory partition size may be temporarily stored in the on-chip memory until an amount corresponding to a full or nearly full partition has been collected, at which point the data can be efficiently written to an external memory partition.

公开(公告)号：WO2022139849A1

公开(公告)日：2022-06-30

申请号：PCT/US2020/067075

申请日：2020-12-26

Applicant: INTEL CORPORATION

Inventor： AGARWAL, Rajat ,  CHEN, Hsing-Min ,  CHEN, Wei P. ,  WU, Wei ,  LING, Jing ,  BAINS, Kuljit ,  CRISS, Kjersten E. ,  BUCH, Deep K. ,  YIGZAW, Theodros ,  HOLM, John G ,  RUDOFF, Andrew M. ,  SINGH, Vaibhav ,  MANDAVA, Sreenivas

IPC: G06F11/10 ,  G11C29/42 ,  G11C29/52 ,  G11C29/00

Abstract: A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.

公开(公告)号：WO2016127143A1

公开(公告)日：2016-08-11

申请号：PCT/US2016/016905

申请日：2016-02-06

Applicant: INTEL CORPORATION

Inventor： DAS, Debaleena ,  HUANG, George H ,  LING, Jing ,  DAFTARI, Reza E ,  GANESAN, Meera

IPC: G06F11/16

CPC classification number: G06F11/1662 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/0647 ,  G06F3/0683 ,  G06F11/00 ,  G06F11/2094 ,  G06F2201/825

Abstract: Memory subsystem error management enables dynamically changing lockstep partnerships. A memory subsystem has a lockstep partnership relationship between a first memory portion and a second memory portion to spread error correction over the pair of memory resources. The lockstep partnership can be preconfigured. In response to detecting a hard error in the lockstep partnership, the memory subsystem can cancel or reverse the lockstep partnership between the first memory portion and the second memory portion and create or set a new lockstep partnership. The detected error can be a second hard error in the lockstep partnership. The memory subsystem can create new lockstep partnerships between the first memory portion and a third memory portion as lockstep partners and between the second memory portion and a fourth memory portion as lockstep partners. The memory subsystem can also be configured to change the granularity of the lockstep partnership when changing partnerships.

Abstract translation: 内存子系统错误管理可实现动态更改的锁步合作伙伴关系。 存储器子系统具有在第一存储器部分和第二存储器部分之间的锁步合作关系，以在所述一对存储器资源上扩展纠错。 锁定合作伙伴关系可以预先配置。 响应于检测锁步伙伴关系中的硬错误，存储器子系统可以取消或反转第一存储器部分和第二存储器部分之间的锁步合作关系，并创建或设置新的锁步伙伴关系。 检测到的错误可能是锁步伙伴关系中的第二个硬错误。 存储器子系统可以在第一存储器部分和第三存储器部分之间创建新的锁步合作关系，作为锁步伙伴，并且在第二存储器部分和作为锁步伙伴的第四存储器部分之间。 内存子系统也可以配置为在更改合作伙伴关系时更改锁步伙伴关系的粒度。

公开(公告)号：WO2003103236A1

公开(公告)日：2003-12-11

申请号：PCT/US2003/015729

申请日：2003-05-08

Applicant: INTEL CORPORATION

Inventor： HUANG, Anguo ,  CAIA, Jean-Michel ,  LING, Jing ,  CALDERON, Juan-Carlos ,  JOSHI, Vivek

IPC: H04L12/56

CPC classification number: H04L47/32 ,  H04L47/10 ,  H04L47/2441 ,  H04L47/30 ,  H04L49/20 ,  H04L49/30 ,  H04L49/90 ,  H04L49/9026

Abstract: Network applications may require a guaranteed rate of throughput, which may be accomplished by using buffer memory reservation to manage a data queue used to store incoming packets. Buffer memory reservation reserves a portion of a data queue as a dedicated queue for each flow, reserves another portion of a data queue as a shared queue, and associates a portion of the shared queue with each flow. The amount of the buffer memory reserved by the dedicated queue sizes and the shared queue portion sizes for all of the flows may exceed the amount of physical memory available to buffer incoming packets.

Abstract translation: 网络应用可能需要保证的吞吐率，这可以通过使用缓冲存储器预留来管理用于存储传入分组的数据队列来实现。 缓冲存储器预留将数据队列的一部分保留为每个流的专用队列，将数据队列的另一部分保留为共享队列，并将共享队列的一部分与每个流相关联。 由专用队列大小保留的缓冲存储器的数量以及所有流的共享队列部分大小可能超过可用于缓冲传入数据包的物理内存量。

公开(公告)号：EP3379420A1

公开(公告)日：2018-09-26

申请号：EP18155593.9

申请日：2018-02-07

Applicant: Intel Corporation

Inventor： CHEN, Wei ,  AGARWAL, Rajat ,  LING, Jing ,  LIU, Daniel W.

IPC: G06F12/0866

CPC classification number: G06F12/0808 ,  G06F1/3287 ,  G06F3/0685 ,  G06F12/0638 ,  G06F12/0811 ,  G06F12/0866 ,  G06F12/0868 ,  G06F12/12 ,  G06F12/128 ,  G06F2212/205 ,  G06F2212/283 ,  G06F2212/621

Abstract: Provided are an apparatus, system, and method to flush modified data from a first memory to a persistent second memory. A first memory controller coupled to the first memory includes at least one RAS controller to read a range of addresses in the first memory. In response to receiving a command from the power control unit, the at least one RAS controller is invoked to read data from at least one range of addresses specified for the RAS controller from the first memory. A second memory controller transfers data read from the first memory determined to be modified to the second memory. The first memory controller sends a signal to the power control unit to indicate that the modified data in the range of addresses specified for the RAS controller was flushed to the second memory in response to the RAS controller completing reading the range of addresses.

公开(公告)号：EP1491021B1

公开(公告)日：2007-10-17

申请号：EP03718095.7

申请日：2003-03-28

Applicant: INTEL CORPORATION

Inventor： HUANG, Anguo ,  LING, Jing ,  CAIA, Jean-Michel ,  CALDERON, Juan-Carlos ,  JOSHI, Vivek

IPC: H04L29/06 ,  H04L12/56

CPC classification number: H04L47/6215 ,  H04L47/10 ,  H04L47/39 ,  H04L47/50 ,  H04L47/521 ,  H04L47/627

Abstract: The rate-based scheduling for a network application is used to control the bandwidth available to a flow while scheduling the transmission of the flow. The rate-based scheduling uses rate credits to represent the amount of data a flow is permitted to transmit and only permits a flow to transmit if the flow has a rate credit available. A flow is permitted to transmit only if the peak packet rate for the scheduler has not been exceeded.

公开(公告)号：EP1508225B1

公开(公告)日：2012-11-07

申请号：EP03726810.9

申请日：2003-05-08

Applicant: Intel Corporation

Inventor： CALDERON, Juan-Carlos ,  LING, Jing ,  CAIA, Jean-Michel ,  JOSHI, Vivek ,  HUANG, Anguo

IPC: H04L12/56

CPC classification number: H04L49/103 ,  H04L49/109 ,  H04L49/254

公开(公告)号：EP3254198A1

公开(公告)日：2017-12-13

申请号：EP16747397.4

申请日：2016-02-06

Applicant: Intel Corporation

Inventor： DAS, Debaleena ,  HUANG, George H ,  LING, Jing ,  DAFTARI, Reza E ,  GANESAN, Meera

IPC: G06F11/16

CPC classification number: G06F11/1662 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/0647 ,  G06F3/0683 ,  G06F11/00 ,  G06F11/2094 ,  G06F2201/825

Abstract: Memory subsystem error management enables dynamically changing lockstep partnerships. A memory subsystem has a lockstep partnership relationship between a first memory portion and a second memory portion to spread error correction over the pair of memory resources. The lockstep partnership can be preconfigured. In response to detecting a hard error in the lockstep partnership, the memory subsystem can cancel or reverse the lockstep partnership between the first memory portion and the second memory portion and create or set a new lockstep partnership. The detected error can be a second hard error in the lockstep partnership. The memory subsystem can create new lockstep partnerships between the first memory portion and a third memory portion as lockstep partners and between the second memory portion and a fourth memory portion as lockstep partners. The memory subsystem can also be configured to change the granularity of the lockstep partnership when changing partnerships.

公开(公告)号：EP1508227B1

公开(公告)日：2008-08-06

申请号：EP03731245.1

申请日：2003-05-08

Applicant: Intel Corporation

Inventor： HUANG, Anguo ,  CAIA, Jean-Michel ,  LING, Jing ,  CALDERON, Juan-Carlos ,  JOSHI, Vivek

IPC: H04L12/56

CPC classification number: H04L47/32 ,  H04L47/10 ,  H04L47/2441 ,  H04L47/30 ,  H04L49/20 ,  H04L49/30 ,  H04L49/90 ,  H04L49/9026

Abstract: Network applications may require a guaranteed rate of throughput, which may be accomplished by using buffer memory reservation to manage a data queue used to store incoming packets. Buffer memory reservation reserves a portion of a data queue as a dedicated queue for each flow, reserves another portion of a data queue as a shared queue, and associates a portion of the shared queue with each flow. The amount of the buffer memory reserved by the dedicated queue sizes and the shared queue portion sizes for all of the flows may exceed the amount of physical memory available to buffer incoming packets.