中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

20 records (took 0.024 seconds)

    EEFICIENT GRAPHICS STATE MANAGEMENT FOR ZONE RENDERING
    1.
    发明申请
    EEFICIENT GRAPHICS STATE MANAGEMENT FOR ZONE RENDERING 审中-公开
    区域渲染的有效图形状态管理

    公开(公告)号：WO2003058557A1

    公开(公告)日：2003-07-17

    申请号：PCT/US2002/040170

    申请日：2002-12-12

    Applicant: INTEL CORPORATION

    Inventor： DOYLE, Peter

    IPC: G06T15/00

    CPC classification number: G06T15/005

    Abstract: The present invention provides a mechanism to track and manage graphics state with hardware state-binning logic for use with the the-based zone rendering method of generating graphical images. Only the current values of the dynamic state variables are maintained in hardware. Dynamic includes, but is not limited to, state variables that are considered likely to change between primitives. The set of dynamic state variables is subdivided into subgroups. Each state group is associated with a per-bin array of tracking bits. Whenever a state change is encountered, the tracking bit corresponding to the associated state group is set for all bins. Prior to placing a primitive in a bin, the tracking bits associated with that bin are examined, and the current state corresponding to set tracking bits is inserted in the bin before the primitive. Then the tracking bits for that bin are cleared.

    Abstract translation: 本发明提供一种用于利用硬件状态分类逻辑来跟踪和管理图形状态的机制，以用于生成图形图像的基于区域的区域渲染方法。 只有硬件中维护动态状态变量的当前值。 动态包括但不限于被认为可能在原语之间变化的状态变量。 一组动态状态变量被细分为子组。 每个状态组与跟踪位的每个二进制数组相关联。 每当遇到状态改变时，对应于相关联的状态组的跟踪位都设置为所有存储区。 在将原语放在一个bin之前，检查与该bin相关联的跟踪位，并且将与设置跟踪位相对应的当前状态插入到该原语之前的bin中。 然后清除该仓的跟踪位。

    DEPTH WRITE DISABLE FOR ZONE RENDERING
    4.
    发明申请
    DEPTH WRITE DISABLE FOR ZONE RENDERING 审中-公开
    深度写阻止区域渲染

    公开(公告)号：WO2003058558A1

    公开(公告)日：2003-07-17

    申请号：PCT/US2002/039776

    申请日：2002-12-11

    Applicant: INTEL CORPORATION

    Inventor： SREENIVAS, Aditya ,  DOYLE, Peter

    IPC: G06T15/40

    CPC classification number: G06T1/60 ,  G06T15/405

    Abstract: A depth write disable apparatus and method for controlling evictions, such as depth values, from a depth cache to a corresponding depth buffer in a zone rendering system. When the depth write disable circuitry is enabled, evictions from the depth cache (as which typically occur during the rendering of the next zone) to the depth buffer are prevented. In particular, once the depth buffer is initialized (i.e.cleared) to a constant value at the beginning of a scene, the depth buffer does not need to be read. The depthcache handles intermediate depth reads and writes within each zone. Since the memory resident depth buffer is not required after a scene is rendered, it never needs to be written. The final depthvalues for a zone can thus be discarded (i.e., rather than written to the depth buffer) after each zone is rendering.

    Abstract translation: 一种深度写入禁止装置和方法，用于控制从区域渲染系统中的深度缓存到相应的深度缓冲区的撤离，例如深度值。 当深度写入禁止电路被使能时，防止从深度缓存（通常在渲染下一个区域期间发生）到深度缓冲区的驱逐。 特别地，一旦深度缓冲器被初始化（即被清除）到场景开始处的恒定值，则不需要读取深度缓冲器。 深度缓存处理每个区域内的中间深度读取和写入。 由于在呈现场景后不需要内存驻留深度缓冲区，因此不需要写入。 因此，在每个区域呈现之后，区域的最终深度值可被丢弃（即，而不是写入深度缓冲区）。

    APPARATUS, METHOD AND SYSTEM WITH A GRAPHICS-RENDERING ENGINE HAVING A GRAPHICS CONTEXT MANAGER
    5.
    发明申请
    APPARATUS, METHOD AND SYSTEM WITH A GRAPHICS-RENDERING ENGINE HAVING A GRAPHICS CONTEXT MANAGER 审中-公开

    公开(公告)号：WO2003003206A3

    公开(公告)日：2003-01-09

    申请号：PCT/US2002/020682

    申请日：2002-06-28

    Applicant: INTEL CORPORATION

    Inventor： DOYLE, Peter ,  SREENIVAS, Aditya

    IPC: G06F9/48

    Abstract: A method, apparatus, and system to concurrently render independent images for display on one or more display devices. In an embodiment, a graphics-rendering engine concurrently renders independent images for display on multiple display devices. A graphics context manager stores in a first memory area and restores from the first memory area information describing a first rendering context associated with a first independent image. The graphics context manager stores in a second memory area and restores from the second memory area information describing a second rendering context associated with a second independent image.

    APPARATUS AND METHOD FOR OPTIMIZED TILE-BASED RENDERING
    6.
    发明申请
    APPARATUS AND METHOD FOR OPTIMIZED TILE-BASED RENDERING 审中-公开
    优化的基于TILE的渲染的装置和方法

    公开(公告)号：WO2018052607A1

    公开(公告)日：2018-03-22

    申请号：PCT/US2017/046845

    申请日：2017-08-15

    Applicant: INTEL CORPORATION

    Inventor： SURTI, Prasoonkumar ,  AKENINE-MOLLER, Tomas G. ,  COWPERTHWAITE, David ,  TIAN, Kevin ,  DOYLE, Peter ,  INSKO, Brent ,  LAKE, Adam T.

    IPC: G06T15/00 ,  G06T1/20 ,  G06T1/60

    Abstract: A virtual reality apparatus and method are described for tile-based rendering. For example, one embodiment of an apparatus comprises: a set of on-chip geometry buffers including a first buffer to store geometry data, and a set of pointer buffers to store pointers to the geometry data; a tile-based immediate mode rendering (TBIMR) module to perform tile-based immediate mode rendering using geometry data and pointers stored within the set of on-chip geometry buffers; spill circuitry to determine when the on-chip geometry buffers are over-subscribed and responsively spill additional geometry data and/or pointers to an off-chip memory; and a prefetcher to start prefetching the geometry data from the off-chip memory as space becomes available within the on-chip geometry buffers, the TBIMR module to perform tile-based immediate mode rendering using the geometry data prefetched from the off-chip memory.

    Abstract translation: 描述了用于基于图块的渲染的虚拟现实设备和方法。 例如，装置的一个实施例包括：一组片上几何缓冲器，其包括用于存储几何数据的第一缓冲器和用于存储指向几何数据的指针的一组指针缓冲器; 基于区块的立即模式渲染（TBIMR）模块，用于使用存储在所述片上几何缓冲区集合内的几何数据和指针来执行基于区块的立即模式渲染; 溢出电路以确定何时片上几何缓冲器过度订购并且响应地将附加几何数据和/或指针溢出到片外存储器; 以及当片上几何缓冲器内的空间变得可用时开始从片外存储器预取几何数据的预取器，TBIMR模块使用从片外存储器预取的几何数据执行基于片的立即模式渲染。

    AUTOMATIC MEMORY MANAGEMENT FOR ZONE RENDERING
    7.
    发明申请
    AUTOMATIC MEMORY MANAGEMENT FOR ZONE RENDERING 审中-公开

    公开(公告)号：WO2003058555A3

    公开(公告)日：2003-07-17

    申请号：PCT/US2002/039791

    申请日：2002-12-11

    Applicant: INTEL CORPORATION

    Inventor： SREENIVAS, Aditya ,  DOYLE, Peter

    IPC: G06T15/00

    Abstract: The present invention optimizes graphics performance during zone rendering by providing an automatic management of bin memory between the binning and rendering phases. Embodiments of the present invention provide a mechanism by which the binner and renderer automatically share a pool of physical memory pages in order to build bin buffers and recycle them after they have been used in rendering. This is performed in such a fashion that multiple binned scenes can be queued up concurrently, with no requirement for software intervention except under exceptional conditions. The need for software management of zone rendering bin buffer memory is thus eliminated. Multiple scenes for binning and rendering can also be queued without software intervention.

    AUTOMATIC MEMORY MANAGEMENT FOR ZONE RENDERING
    8.
    发明申请
    AUTOMATIC MEMORY MANAGEMENT FOR ZONE RENDERING 审中-公开
    区域渲染的自动记忆管理

    公开(公告)号：WO2003058555A2

    公开(公告)日：2003-07-17

    申请号：PCT/US2002/039791

    申请日：2002-12-11

    Applicant: INTEL CORPORATION

    Inventor： SREENIVAS, Aditya ,  DOYLE, Peter

    IPC: G06T11/00

    CPC classification number: G06T1/60 ,  G06T15/04

    Abstract: The present invention optimizes graphics performance during zone rendering by providing an automatic management of bin memory between the binning and rendering phases. Embodiments of the present invention provide a mechanism by which the binner and renderer automatically share a pool of physical memory pages in order to build bin buffers and recycle them after they have been used in rendering. This is performed in such a fashion that multiple binned scenes can be queued up concurrently, with no requirement for software intervention except under exceptional conditions. The need for software management of zone rendering bin buffer memory is thus eliminated. Multiple scenes for binning and rendering can also be queued without software intervention.

    Abstract translation: 本发明通过在分箱和渲染阶段之间提供bin存储器的自动管理来优化区域渲染期间的图形性能。 本发明的实施例提供了一种机制，通过该机制，虚拟机和渲染器自动共享物理存储器页面池，以便构建bin缓冲器并在渲染后使用它们。 这样做的方式是，可以将多个分箱的场景同时排队，除非在特殊情况下不需要软件干预。 因此消除了对区域渲染bin缓冲存储器的软件管理的需要。 用于分档和渲染的多个场景也可以排队等待，无需软件干预。

    APPARATUS, METHOD AND SYSTEM WITH A GRAPHICS-RENDERING ENGINE HAVING A TIME ALLOCATOR
    9.
    发明申请
    APPARATUS, METHOD AND SYSTEM WITH A GRAPHICS-RENDERING ENGINE HAVING A TIME ALLOCATOR 审中-公开
    具有时间分配器的具有图形绘制引擎的装置，方法和系统

    公开(公告)号：WO2003003313A2

    公开(公告)日：2003-01-09

    申请号：PCT/US2002/020781

    申请日：2002-06-28

    Applicant: INTEL CORPORATION

    Inventor： DOYLE, Peter ,  SREENIVAS, Aditya

    IPC: G06T17/00

    CPC classification number: G06F3/1431 ,  G06T15/005

    Abstract: A method, apparatus, and system to concurrently render independent images for display on one or more display devices. In an embodiment, a graphics-rendering engine concurrently renders independent images for display on multiple display devices. A time allocator arbitrates the concurrent use of the graphics-rendering engine between each independent image being rendered.

    Abstract translation: 用于同时呈现独立图像以在一个或多个显示设备上显示的方法，设备和系统。 在一个实施例中，图形渲染引擎同时渲染独立图像以在多个显示设备上显示。 时间分配器对每个独立图像之间的图形渲染引擎的并发使用进行仲裁。

Patent Agency Ranking