公开(公告)号：US11593292B2

公开(公告)日：2023-02-28

申请号：US16894437

申请日：2020-06-05

Applicant: INTEL CORPORATION

Inventor： Patrick Connor ,  Matthew A. Jared ,  Duke C. Hong ,  Elizabeth M. Kappler ,  Chris Pavlas ,  Scott P. Dubal

IPC: G06F13/00 ,  G06F13/40

Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address. The many-to-many and many-to-one peripheral switches forwards the transaction packets internally within the switch based on the destination address such that the packets are forwarded to a node via which the memory address can be accessed. The platform architectures may also be configured to support migration operations in response to failure or replacement of a node.

公开(公告)号：US10684973B2

公开(公告)日：2020-06-16

申请号：US14014775

申请日：2013-08-30

Applicant: Intel Corporation

Inventor： Patrick Connor ,  Matthew A. Jared ,  Duke C. Hong ,  Elizabeth M. Kappler ,  Chris Pavlas ,  Scott P. Dubal

IPC: G06F13/28 ,  G06F13/40

Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address. The many-to-many and many-to-one peripheral switches forwards the transaction packets internally within the switch based on the destination address such that the packets are forwarded to a node via which the memory address can be accessed. The platform architectures may also be configured to support migration operations in response to failure or replacement of a node.

公开(公告)号：US09047417B2

公开(公告)日：2015-06-02

申请号：US13663131

申请日：2012-10-29

Applicant: Intel Corporation

Inventor： Patrick Conner ,  Chris Pavlas ,  Elizabeth M. Kappler ,  Matthew A. Jared ,  Duke C. Hong ,  Scott P. Dubal

IPC: H04L12/54 ,  G06F13/40 ,  H04L12/24 ,  H04L29/08 ,  H04L12/801

CPC classification number: G06F13/4027 ,  H04L12/56 ,  H04L41/08 ,  H04L47/10 ,  H04L47/33 ,  H04L67/10 ,  H04L69/321

Abstract: Methods, apparatus, and computer platforms and architectures employing node aware network interfaces are disclosed. The methods and apparatus may be implemented on computer platforms such as those employing a Non-uniform Memory Access (NUMA) architecture including a plurality of nodes, each node comprising a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a NUMA aware Network Interface Controller (NIC). Under one method, a packet is received from a network at a first NIC comprising a component of a first node, and a determination is made that packet data for the packet is to be forwarded to a second node including a second NIC. The packet data is then forwarded from the first NIC to the second NIC via a NIC-to-NIC interconnect link. Upon being received at the second NIC, processing of the packet (data) is handled as if the packet was received from the network at the second NIC.

Abstract translation: 公开了采用节点感知网络接口的方法，装置和计算机平台和架构。 方法和装置可以在诸如使用包括多个节点的非均匀存储器访问（NUMA）架构的计算机平台上实现，每个节点包括多个部件，包括具有至少一个级别的存储器高速缓存的处理器 可操作地耦合到系统存储器并且可操作地耦合到NUMA感知网络接口控制器（NIC）。 在一种方法下，从包括第一节点的组件的第一NIC处的网络接收分组，并且确定该分组的分组数据将被转发到包括第二NIC的第二节点。 然后，分组数据经由NIC至NIC互连链路从第一NIC转发到第二NIC。 在第二NIC被接收时，分组（数据）的处理被处理，好像在第二NIC处从网络接收到分组。

公开(公告)号：US11960429B2

公开(公告)日：2024-04-16

申请号：US18082485

申请日：2022-12-15

Applicant: Intel Corporation

Inventor： Patrick Connor ,  Matthew A. Jared ,  Duke C. Hong ,  Elizabeth M. Kappler ,  Chris Pavlas ,  Scott P. Dubal

IPC: G06F13/00 ,  G06F13/40

CPC classification number: G06F13/4022

Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address. The many-to-many and many-to-one peripheral switches forwards the transaction packets internally within the switch based on the destination address such that the packets are forwarded to a node via which the memory address can be accessed. The platform architectures may also be configured to support migration operations in response to failure or replacement of a node.

公开(公告)号：US20200301864A1

公开(公告)日：2020-09-24

申请号：US16894437

申请日：2020-06-05

Applicant: INTEL CORPORATION

Inventor： Patrick Connor ,  Matthew A. Jared ,  Duke C. Hong ,  Elizabeth M. Kappler ,  Chris Pavlas ,  Scott P. Dubal

IPC: G06F13/40

Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address. The many-to-many and many-to-one peripheral switches forwards the transaction packets internally within the switch based on the destination address such that the packets are forwarded to a node via which the memory address can be accessed. The platform architectures may also be configured to support migration operations in response to failure or replacement of a node.

公开(公告)号：US20180091447A1

公开(公告)日：2018-03-29

申请号：US15274337

申请日：2016-09-23

Applicant: Intel Corporation

Inventor： Matthew A. Jared ,  Duke C. Hong ,  Manasi Deval

IPC: H04L12/861 ,  H04L12/869 ,  H04L12/801 ,  H04L12/26

CPC classification number: H04L49/9005 ,  H04L43/08 ,  H04L43/0817 ,  H04L47/11 ,  H04L47/58

Abstract: Technologies for dynamically transitioning network traffic host buffers of a network computing device include the software abstraction of one or more hardware queues of the network computing device based on a network flow type associated with network traffic received by the network computing device. The network computing device is configured to identify a queue transition event, completing pending transactions in one or more of the software abstracted queues, and transition the abstracted queues to handle the flow type associated with the queue transition event. Additionally, the network computing device is configured to realign the abstracted queues to be associated with one or more hardware components of the network computing device based on the second network traffic flow type, provide a ready indication to a client associated with the abstracted queues that indicates the abstracted queues are ready for polling, and process received network traffic associated with the second network traffic flow type in the abstracted queues. Other embodiments are described herein.

公开(公告)号：US09471350B2

公开(公告)日：2016-10-18

申请号：US14037814

申请日：2013-09-26

Applicant: Intel Corporation

Inventor： Chris Pavlas ,  Duke C. Hong ,  Scott P. Dubal ,  Elizabeth M. Kappler ,  Patrick Connor ,  Matthew A. Jared

IPC: G06F9/455 ,  G06Q10/06

CPC classification number: G06F9/45533 ,  G06F9/45558 ,  G06F2009/4557 ,  G06Q10/06315

Abstract: Methods, apparatus, software, and system architectures for supporting virtualized system migrations and scaling. Under aspects of a method, data is automatically collected and aggregated at multiple levels by a plurality of agents for each of multiple data centers. The data includes data relating to virtual machine utilization, data relating to electrical utilization costs, data relating to data center utilization, and data relating to triggers events. The data is processed to determine whether to migrate virtual servers from a first data center to a second data center. The software architecture includes a plurality of modules including a controller, data center profile, transition triggers, power cost profile, and virtual machine package module. The agents are implemented in an agent hierarchy and configured to collect data themselves and/or aggregate data from other agents and provide an API to facilitate access to collected data and agent services.

Abstract translation: 用于支持虚拟化系统迁移和缩放的方法，设备，软件和系统架构。 在方法的方面，数据被多个级别自动地收集和聚合，由多个代理针对多个数据中心中的每一个。 数据包括与虚拟机利用有关的数据，与电力利用成本有关的数据，与数据中心利用有关的数据以及与触发事件有关的数据。 处理数据以确定是否将虚拟服务器从第一个数据中心迁移到第二个数据中心。 软件架构包括多个模块，包括控制器，数据中心配置文件，转换触发器，电源成本配置文件和虚拟机包模块。 代理在代理层级中实现，并被配置为自己收集数据和/或从其他代理聚合数据，并提供API以便于访问收集的数据和代理服务。