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公开(公告)号：US11032357B2
公开(公告)日：2021-06-08
申请号：US15474587
申请日：2017-03-30
Applicant: Intel Corporation
Inventor： Karthik Veeramani , Ujwal Paidipathi , Rajneesh Chowdhury , Prakash N. Iyer , Maciej Machnikowski , Chris Pavlas , Scott P. Dubal
Abstract: Systems, apparatuses, and/or methods to provide data processing offload. An apparatus may determine whether a task is to be processed locally at a client device or remotely off the client device and issue the task to a wireless network and/or a wired network when the task is to be processed remotely off the client device at a server device. An apparatus may identify the task from the wireless network and/or the wired network when the task is to be processed locally at the server device, distribute the task to a server resource at the server device when the task is to be to processed locally at the service device, and provide a result of the task to the wireless network and/or the wired network when the result is to be consumed remotely at the client device.
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公开(公告)号：US10684973B2
公开(公告)日：2020-06-16
申请号：US14014775
申请日：2013-08-30
Applicant: Intel Corporation
Inventor： Patrick Connor , Matthew A. Jared , Duke C. Hong , Elizabeth M. Kappler , Chris Pavlas , Scott P. Dubal
Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address. The many-to-many and many-to-one peripheral switches forwards the transaction packets internally within the switch based on the destination address such that the packets are forwarded to a node via which the memory address can be accessed. The platform architectures may also be configured to support migration operations in response to failure or replacement of a node.
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公开(公告)号：US20200301864A1
公开(公告)日：2020-09-24
申请号：US16894437
申请日：2020-06-05
Applicant: INTEL CORPORATION
Inventor： Patrick Connor , Matthew A. Jared , Duke C. Hong , Elizabeth M. Kappler , Chris Pavlas , Scott P. Dubal
IPC: G06F13/40
Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address. The many-to-many and many-to-one peripheral switches forwards the transaction packets internally within the switch based on the destination address such that the packets are forwarded to a node via which the memory address can be accessed. The platform architectures may also be configured to support migration operations in response to failure or replacement of a node.
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公开(公告)号：US09471350B2
公开(公告)日：2016-10-18
申请号：US14037814
申请日：2013-09-26
Applicant: Intel Corporation
Inventor： Chris Pavlas , Duke C. Hong , Scott P. Dubal , Elizabeth M. Kappler , Patrick Connor , Matthew A. Jared
CPC classification number: G06F9/45533 , G06F9/45558 , G06F2009/4557 , G06Q10/06315
Abstract: Methods, apparatus, software, and system architectures for supporting virtualized system migrations and scaling. Under aspects of a method, data is automatically collected and aggregated at multiple levels by a plurality of agents for each of multiple data centers. The data includes data relating to virtual machine utilization, data relating to electrical utilization costs, data relating to data center utilization, and data relating to triggers events. The data is processed to determine whether to migrate virtual servers from a first data center to a second data center. The software architecture includes a plurality of modules including a controller, data center profile, transition triggers, power cost profile, and virtual machine package module. The agents are implemented in an agent hierarchy and configured to collect data themselves and/or aggregate data from other agents and provide an API to facilitate access to collected data and agent services.
Abstract translation: 用于支持虚拟化系统迁移和缩放的方法，设备，软件和系统架构。 在方法的方面，数据被多个级别自动地收集和聚合，由多个代理针对多个数据中心中的每一个。 数据包括与虚拟机利用有关的数据，与电力利用成本有关的数据，与数据中心利用有关的数据以及与触发事件有关的数据。 处理数据以确定是否将虚拟服务器从第一个数据中心迁移到第二个数据中心。 软件架构包括多个模块，包括控制器，数据中心配置文件，转换触发器，电源成本配置文件和虚拟机包模块。 代理在代理层级中实现，并被配置为自己收集数据和/或从其他代理聚合数据，并提供API以便于访问收集的数据和代理服务。
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公开(公告)号：US20160173351A1
公开(公告)日：2016-06-16
申请号：US14568789
申请日：2014-12-12
Applicant: Intel Corporation
Inventor： Scott P. Dubal , Patrick Connor , Chris Pavlas
Abstract: One embodiment provides a network adapter. The network adapter includes a network adapter controller, a medium access controller (MAC) and a physical layer (PHY) including at least one port. The network adapter further includes optical communication logic to at least one of receive and/or acquire a local alert and generate a local alert message related to the local alert, the local alert message including an alert identifier (ID) and a network adapter ID. The network adapter further includes a first light emitting diode (LED) to convert the local alert message to a corresponding optical local alert message and to transmit the optical local alert message to an optical communication path.
Abstract translation: 一个实施例提供一种网络适配器。 网络适配器包括网络适配器控制器，媒体接入控制器（MAC）和包括至少一个端口的物理层（PHY）。 网络适配器还包括光通信逻辑，用于接收和/或获取本地警报中的至少一个，并且生成与本地警报相关的本地警报消息，本地警报消息包括警报标识符（ID）和网络适配器ID。 网络适配器还包括第一发光二极管（LED），用于将本地警报消息转换为对应的光学本地警报消息，并将光学本地警报消息发送到光通信路径。
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Patent Agency Ranking
公开(公告)号：US20230176987A1
公开(公告)日：2023-06-08
申请号：US18082485
申请日：2022-12-15
Applicant: Intel Corporation
Inventor： Patrick Connor , Matthew A. JARED , Duke C. HONG , Elizabeth M. KAPPLER , Chris Pavlas , Scott P. Dubal
IPC: G06F13/40
CPC classification number: G06F13/4022
Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address. The many-to-many and many-to-one peripheral switches forwards the transaction packets internally within the switch based on the destination address such that the packets are forwarded to a node via which the memory address can be accessed. The platform architectures may also be configured to support migration operations in response to failure or replacement of a node.
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公开(公告)号：US11593292B2
公开(公告)日：2023-02-28
申请号：US16894437
申请日：2020-06-05
Applicant: INTEL CORPORATION
Inventor： Patrick Connor , Matthew A. Jared , Duke C. Hong , Elizabeth M. Kappler , Chris Pavlas , Scott P. Dubal
Abstract: Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address. The many-to-many and many-to-one peripheral switches forwards the transaction packets internally within the switch based on the destination address such that the packets are forwarded to a node via which the memory address can be accessed. The platform architectures may also be configured to support migration operations in response to failure or replacement of a node.
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公开(公告)号：US11550606B2
公开(公告)日：2023-01-10
申请号：US16131012
申请日：2018-09-13
Applicant: Intel Corporation
Inventor： Patrick Connor , Scott Dubal , Chris Pavlas , Katalin Bartfai-Walcott , Amritha Nambiar , Sharada Ashok Shiddibhavi
Abstract: Technologies for deploying virtual machines (VMs) in a virtual network function (VNF) infrastructure include a compute device configured to collect a plurality of performance metrics based on a set of key performance indicators, determine a key performance indicator value for each of the set of key performance indicators based on the collected plurality of performance metrics, and determine a service quality index for a virtual machine (VM) instance of a plurality of VM instances managed by the compute as a function each key performance indicator value. Additionally, the compute device is configured to determine whether the determined service quality index is acceptable and perform, in response to a determination that the determined service quality index is not acceptable, an optimization action to ensure the VM instance is deployed on an acceptable host of the compute device. Other embodiments are described herein.
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公开(公告)号：US20180181421A1
公开(公告)日：2018-06-28
申请号：US15391777
申请日：2016-12-27
Applicant: Intel Corporation
Inventor： Patrick Connor , Scott P. Dubal , James R. Hearn , Iosif Gasparakis , Chris Pavlas , Eliezer Tamir
CPC classification number: G06F9/45558 , G06F9/54 , G06F15/17306 , G06F2009/45583
Abstract: An example computer system for transferring a packet includes a hypervisor to run a first virtual machine and a second virtual machine. The computer system also includes a first memory address space associated with the first virtual machine to store the packet. The computer system further includes a second memory address space associated with the second virtual machine to receive and store the packet. The computer system also includes a virtual switch coupled to the first virtual machine and the second virtual machine to detect that the packet is to be sent from the first virtual machine to the second virtual machine. The computer system further includes a direct memory access device to copy the packet from the first memory address space to the second memory address space via the direct memory access device.
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10.发明授权公开(公告)号：US10423783B2
公开(公告)日：2019-09-24
申请号：US15383906
申请日：2016-12-19
Applicant: Intel Corporation
Inventor： Chris Pavlas , James R. Hearn , Scott P. Dubal , Patrick Connor
Abstract: Methods and apparatus to recover a processor state during a system failure or security event are disclosed. An example apparatus to recover data includes a processor including a local memory and a system monitor in communication with the processor. The system monitor is to copy processor backup data to a non-volatile memory in response to a processor backup event. The processor backup data includes contents of the local memory.
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