公开(公告)号：WO2016099811A1

公开(公告)日：2016-06-23

申请号：PCT/US2015/062029

申请日：2015-11-21

Applicant: INTEL CORPORATION

Inventor： ADLER, Robert P. ,  EDIRISOORIYA, Geetani R. ,  MURRAY, Joseph ,  BUCH, Deep K.

IPC: G06F11/10

CPC classification number: H04L1/0045 ,  H04L1/0063 ,  H04L12/40 ,  H04L12/40045 ,  H04L2001/0094

Abstract: An inbound sideband interface is provided to receive a message over a first sideband link, and parity logic is provided to calculate a parity bit for the message. Further, an outbound sideband interface is provided to forward the message to another device over a second sideband link. The second sideband link includes a plurality of data wires and a parity bit wire. The message is forwarded over at least some of the data wires and the parity bit is sent to the other device over the parity bit wire to correspond with the message.

Abstract translation: 提供入站边带接口以通过第一边带链路接收消息，并且提供奇偶校验逻辑以计算消息的奇偶校验位。 此外，提供出站边带接口以通过第二边带链路将消息转发到另一设备。 第二边带链路包括多条数据线和奇偶位线。 消息通过至少一些数据线转发，并且奇偶校验位通过奇偶校验位线发送到另一设备以对应于消息。

公开(公告)号：EP3234777B1

公开(公告)日：2020-03-11

申请号：EP15870612.7

申请日：2015-11-21

Applicant: INTEL Corporation

Inventor： ADLER, Robert P. ,  EDIRISOORIYA, Geetani R. ,  MURRAY, Joseph ,  BUCH, Deep K.

IPC: G06F11/10

公开(公告)号：EP3234777A1

公开(公告)日：2017-10-25

申请号：EP15870612.7

申请日：2015-11-21

Applicant: INTEL Corporation

Inventor： ADLER, Robert P. ,  EDIRISOORIYA, Geetani R. ,  MURRAY, Joseph ,  BUCH, Deep K.

IPC: G06F11/10

CPC classification number: H04L1/0045 ,  H04L1/0063 ,  H04L12/40 ,  H04L12/40045 ,  H04L2001/0094

Abstract: An inbound sideband interface is provided to receive a message over a first sideband link, and parity logic is provided to calculate a parity bit for the message. Further, an outbound sideband interface is provided to forward the message to another device over a second sideband link. The second sideband link includes a plurality of data wires and a parity bit wire. The message is forwarded over at least some of the data wires and the parity bit is sent to the other device over the parity bit wire to correspond with the message.

Abstract translation: 提供入境边带接口以通过第一边带链路接收消息，并提供奇偶校验逻辑以计算消息的奇偶校验位。 此外，提供出站边带接口以通过第二边带链路将消息转发到另一设备。 第二边带链路包括多条数据线和奇偶校验位线。 该消息通过至少一些数据线被转发，并且奇偶校验位通过奇偶校验位线被发送到另一个设备以与该消息相对应。