公开(公告)号：WO2016099811A1

公开(公告)日：2016-06-23

申请号：PCT/US2015/062029

申请日：2015-11-21

Applicant: INTEL CORPORATION

Inventor： ADLER, Robert P. ,  EDIRISOORIYA, Geetani R. ,  MURRAY, Joseph ,  BUCH, Deep K.

IPC: G06F11/10

CPC classification number: H04L1/0045 ,  H04L1/0063 ,  H04L12/40 ,  H04L12/40045 ,  H04L2001/0094

Abstract: An inbound sideband interface is provided to receive a message over a first sideband link, and parity logic is provided to calculate a parity bit for the message. Further, an outbound sideband interface is provided to forward the message to another device over a second sideband link. The second sideband link includes a plurality of data wires and a parity bit wire. The message is forwarded over at least some of the data wires and the parity bit is sent to the other device over the parity bit wire to correspond with the message.

Abstract translation: 提供入站边带接口以通过第一边带链路接收消息，并且提供奇偶校验逻辑以计算消息的奇偶校验位。 此外，提供出站边带接口以通过第二边带链路将消息转发到另一设备。 第二边带链路包括多条数据线和奇偶位线。 消息通过至少一些数据线转发，并且奇偶校验位通过奇偶校验位线发送到另一设备以对应于消息。

公开(公告)号：WO2022139849A1

公开(公告)日：2022-06-30

申请号：PCT/US2020/067075

申请日：2020-12-26

Applicant: INTEL CORPORATION

Inventor： AGARWAL, Rajat ,  CHEN, Hsing-Min ,  CHEN, Wei P. ,  WU, Wei ,  LING, Jing ,  BAINS, Kuljit ,  CRISS, Kjersten E. ,  BUCH, Deep K. ,  YIGZAW, Theodros ,  HOLM, John G ,  RUDOFF, Andrew M. ,  SINGH, Vaibhav ,  MANDAVA, Sreenivas

IPC: G06F11/10 ,  G11C29/42 ,  G11C29/52 ,  G11C29/00

Abstract: A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.

公开(公告)号：WO2015048023A1

公开(公告)日：2015-04-02

申请号：PCT/US2014/056993

申请日：2014-09-23

Applicant: INTEL CORPORATION

Inventor： SADE, Raanan ,  GABOR, Ron ,  BUCH, Deep K. ,  YIGZAW, Theodros ,  SHWARTSMAN, Stanislav

IPC: G06F11/08 ,  G06F12/00

CPC classification number: G06F11/073 ,  G06F11/0793 ,  G06F11/08

Abstract: Mechanisms for handling multiple data errors that occur simultaneously are provided. A processing device may determine whether multiple data errors occur in memory locations that are within a range of memory locations. If the multiple memory locations are within the range of memory locations, the processing device may continue with a recovery process. If one of the multiple memory locations is outside of the range of memory locations, the processing device may halt the recovery process.

Abstract translation: 提供了同时处理多个数据错误的机制。 处理设备可以确定在存储器位置范围内的存储器位置中是否发生多个数据错误。 如果多个存储器位置在存储器位置的范围内，则处理设备可以继续恢复过程。 如果多个存储器位置中的一个位于存储器位置的范围之外，则处理设备可以停止恢复过程。

公开(公告)号：EP3234777B1

公开(公告)日：2020-03-11

申请号：EP15870612.7

申请日：2015-11-21

Applicant: INTEL Corporation

Inventor： ADLER, Robert P. ,  EDIRISOORIYA, Geetani R. ,  MURRAY, Joseph ,  BUCH, Deep K.

IPC: G06F11/10

公开(公告)号：EP3234777A1

公开(公告)日：2017-10-25

申请号：EP15870612.7

申请日：2015-11-21

Applicant: INTEL Corporation

Inventor： ADLER, Robert P. ,  EDIRISOORIYA, Geetani R. ,  MURRAY, Joseph ,  BUCH, Deep K.

IPC: G06F11/10

CPC classification number: H04L1/0045 ,  H04L1/0063 ,  H04L12/40 ,  H04L12/40045 ,  H04L2001/0094

Abstract: An inbound sideband interface is provided to receive a message over a first sideband link, and parity logic is provided to calculate a parity bit for the message. Further, an outbound sideband interface is provided to forward the message to another device over a second sideband link. The second sideband link includes a plurality of data wires and a parity bit wire. The message is forwarded over at least some of the data wires and the parity bit is sent to the other device over the parity bit wire to correspond with the message.

Abstract translation: 提供入境边带接口以通过第一边带链路接收消息，并提供奇偶校验逻辑以计算消息的奇偶校验位。 此外，提供出站边带接口以通过第二边带链路将消息转发到另一设备。 第二边带链路包括多条数据线和奇偶校验位线。 该消息通过至少一些数据线被转发，并且奇偶校验位通过奇偶校验位线被发送到另一个设备以与该消息相对应。