公开(公告)号：WO2017111769A1

公开(公告)日：2017-06-29

申请号：PCT/US2015/000160

申请日：2015-12-22

Applicant: INTEL CORPORATION

Inventor： KAMGAING, Telesphor ,  DOGIAMIS, Georgios, C. ,  NAIR, Vijay, K. ,  FALCON, Javier, A. ,  LIFF, Shawna, M. ,  TOMITA, Yoshihiro

IPC: H01L23/66 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/48 ,  H01L23/66 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/15192 ,  H01L2924/15321 ,  H01L2924/18161 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104

Abstract: Embodiments of the invention include a microelectronic device that includes a first silicon based substrate having compound semiconductor components. The microelectronic device also includes a second substrate coupled to the first substrate. The second substrate includes an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher.

Abstract translation: 本发明的实施例包括微电子器件，其包括具有化合物半导体组件的第一硅基衬底。 微电子器件还包括耦合到第一衬底的第二衬底。 第二基板包括用于以大约4GHz或更高的频率发送和接收通信的天线单元。

公开(公告)号：WO2018231241A1

公开(公告)日：2018-12-20

申请号：PCT/US2017/037808

申请日：2017-06-16

Applicant: INTEL CORPORATION

Inventor： ELSHERBINI, Adel, A. ,  SOTO GONZALEZ, Javier ,  SWAN, Johanna, M. ,  LIFF, Shawna ,  FALCON, Javier, A. ,  ROBERTS, Jeanette, M. ,  CAUDILLO, Roman ,  CLARKE, James, S. ,  NAM, Ye, Seul

IPC: G06N99/00 ,  B82Y10/00

Abstract: Disclosed herein are qubit device packages, as well as related computing devices and methods. An exemplary qubit device package includes a quantum die and a package substrate. The face of the quantum die that houses one or more quantum circuit components is electrically connected to the package substrate by first level interconnects in the form of conductive pillars. Implementing the first level interconnects as conductive pillars allows providing sufficient distance between the quantum die and the package substrate to reduce TLS losses caused by the package substrate while, at the same time, keeping the overall footprint of the interconnects relatively small, thus providing a scalable approach to reducing quantum losses. In addition, the relatively small footprint of the conductive pillars allows providing them sufficiently close to one another to ensure improved isolation/shielding between different signal lines.

公开(公告)号：WO2017111766A1

公开(公告)日：2017-06-29

申请号：PCT/US2015/000156

申请日：2015-12-22

Applicant: INTEL CORPORATION ,  DOGIAMIS, Georgios, C. ,  KAMGAING, Telesphor ,  LI, Eric, J. ,  FALCON, Javier, A.

Inventor： DOGIAMIS, Georgios, C. ,  KAMGAING, Telesphor ,  LI, Eric, J. ,  FALCON, Javier, A. ,  TOMITA, Yoshihiro ,  NAIR, Vijay, K. ,  LIFF, Shawna, M.

IPC: H01L23/58

CPC classification number: H01L23/58 ,  H01L23/66

Abstract: Embodiments of the invention include a microelectronic device that includes a first die having a silicon based substrate and a second die coupled to the first die. In one example, the second die is formed with compound semiconductor materials. The microelectronic device includes a substrate that is coupled to the first die with a plurality of electrical connections. The substrate including an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher.

Abstract translation: 本发明的实施例包括微电子器件，其包括具有硅基衬底的第一管芯和耦合到第一管芯的第二管芯。 在一个示例中，第二管芯由化合物半导体材料形成。 微电子器件包括通过多个电连接与第一管芯耦合的衬底。 该基片包括一个天线单元，用于以大约4GHz或更高的频率发送和接收通信。