公开(公告)号：US11955426B2

公开(公告)日：2024-04-09

申请号：US17839337

申请日：2022-06-13

Applicant: INTEL CORPORATION

Inventor： Huong Do ,  Kaladhar Radhakrishnan ,  Krishna Bharath ,  Yikang Deng ,  Amruthavalli P. Alur

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/66 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/66 ,  H01L28/10 ,  H01L2223/6672

Abstract: A microelectronics package comprising a substrate, the substrate comprising a dielectric and at least first and second conductor level within the dielectric, where the first and second conductor levels are separated by at least one dielectric layer. The microelectronics package comprises an inductor structure that comprises a magnetic core. The magnetic core is at least partially embedded within the dielectric. The inductor structure comprises a first trace in the first conductor level, a second trace in the second conductor level, and a via interconnect connecting the first and second traces. The first trace and the second trace extend at least partially within the magnetic core.

公开(公告)号：US20200066634A1

公开(公告)日：2020-02-27

申请号：US16107757

申请日：2018-08-21

Applicant: Intel Corporation

Inventor： Huong Do ,  Kaladhar Radhakrishnan ,  Krishna Bharath ,  Yikang Deng ,  Amruthavalli P. Alur

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L23/66

Abstract: A microelectronics package comprising a substrate, the substrate comprising a dielectric and at least first and second conductor level within the dielectric, where the first and second conductor levels are separated by at least one dielectric layer. The microelectronics package comprises an inductor structure that comprises a magnetic core. The magnetic core is at least partially embedded within the dielectric. The inductor structure comprises a first trace in the first conductor level, a second trace in the second conductor level, and a via interconnect connecting the first and second traces. The first trace and the second trace extend at least partially within the magnetic core.

公开(公告)号：US12154710B2

公开(公告)日：2024-11-26

申请号：US17025537

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Anuj Modi ,  Huong Do ,  William J. Lambert ,  Krishna Bharath ,  Harish Krishnamurthy

IPC: H01F27/24 ,  H01F30/06

Abstract: Embodiments disclosed herein include power transformers for microelectronic devices. In an embodiment, a power transformer comprises a magnetic core that is a closed loop with an inner dimension and an outer dimension, and a primary winding around the magnetic core. In an embodiment, the primary winding has a first number of first turns connected in series around the magnetic core. In an embodiment, a secondary winding is around the magnetic core, and the secondary winding has a second number of second turns around the magnetic core. In an embodiment, individual ones of the second turns comprise a plurality of secondary segments connected in parallel.

公开(公告)号：US20220310512A1

公开(公告)日：2022-09-29

申请号：US17839337

申请日：2022-06-13

Applicant: INTEL CORPORATION

Inventor： Huong Do ,  Kaladhar Radhakrishnan ,  Krishna Bharath ,  Yikang Deng ,  Amruthavalli P. Alur

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/66 ,  H01L21/768

Abstract: A microelectronics package comprising a substrate, the substrate comprising a dielectric and at least first and second conductor level within the dielectric, where the first and second conductor levels are separated by at least one dielectric layer. The microelectronics package comprises an inductor structure that comprises a magnetic core. The magnetic core is at least partially embedded within the dielectric. The inductor structure comprises a first trace in the first conductor level, a second trace in the second conductor level, and a via interconnect connecting the first and second traces. The first trace and the second trace extend at least partially within the magnetic core.

公开(公告)号：US20200066830A1

公开(公告)日：2020-02-27

申请号：US16107778

申请日：2018-08-21

Applicant: Intel Corporation

Inventor： Krishna Bharath ,  Wei-Lun Jen ,  Huong Do ,  Amruthavalli Alur

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/64 ,  H01F27/26 ,  H01L23/00

Abstract: A microelectronics package comprises a substrate comprising at least two conductive layers that are separated by a first dielectric. At least one island comprising a magnetic material is embedded within the dielectric between the two conductive layers. An inductor structure extends within a via in the at least one island. The via extends between the two conductive layers. The inductor structure comprises a conductive wall along a sidewall of the via, and wherein the conductive wall surrounds a second dielectric and is electrically coupled to the two conductive layers.

公开(公告)号：US11676950B2

公开(公告)日：2023-06-13

申请号：US16635147

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： Krishna Bharath ,  Sriram Srinivasan ,  Amruthavalli Alur ,  Kaladhar Radhakrishnan ,  Huong Do ,  William Lambert

IPC: H01L23/498 ,  H01L23/64 ,  H01L25/065 ,  H01L25/16

CPC classification number: H01L25/16 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/642 ,  H01L23/645

Abstract: An apparatus is provided which comprises: a plurality of plated through holes; a material with magnetic properties adjacent to the plurality of plated through holes; and one or more conductors orthogonal to a length of the plurality of plated through holes, the one or more conductors to couple one plated through hole of the plurality with another plated through hole of the plurality such that an inductor is formed.

公开(公告)号：US11335620B2

公开(公告)日：2022-05-17

申请号：US16035129

申请日：2018-07-13

Applicant: Intel Corporation

Inventor： Michael J. Hill ,  Anne Augustine ,  Huong Do ,  William Lambert

IPC: H01L23/367 ,  H01L23/64 ,  H01L23/32 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/522

Abstract: Embodiments include a microelectronic device package structure having an inductor at least partially embedded within a substrate. At least one thermal solution structure may be on a surface of the inductor, and may be thermally coupled with the inductor. The one or more thermal solution structures provide a thermal pathway for cooling for the inductor, and extend a thermal time constant of the inductor.

公开(公告)号：US20210098436A1

公开(公告)日：2021-04-01

申请号：US16635147

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： Krishna Bharath ,  Sriram Srinivasan ,  Amruthavalli Alur ,  Kaladhar Radhakrishnan ,  Huong Do ,  William Lambert

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/64

Abstract: An apparatus is provided which comprises: a plurality of plated through holes; a material with magnetic properties adjacent to the plurality of plated through holes; and one or more conductors orthogonal to a length of the plurality of plated through holes, the one or more conductors to couple one plated through hole of the plurality with another plated through hole of the plurality such that an inductor is formed.

公开(公告)号：US20200066627A1

公开(公告)日：2020-02-27

申请号：US16108953

申请日：2018-08-22

Applicant: INTEL CORPORATION

Inventor： Huong Do ,  Kaladhar Radhakrishnan ,  Krishna Bharath ,  Yikang Deng ,  Amruthavalli P. Alur

IPC: H01L23/498 ,  H01F17/00 ,  H01L21/48 ,  H01L23/522 ,  H01L23/58 ,  H01L49/02 ,  H01L23/64

Abstract: A microelectronics package comprises a substrate that comprises a dielectric and at least two conductor layers within the dielectric, and an inductor structure having a magnetic core at least partially within the dielectric and extending at least between a first conductor layer and a second conductor layer. The inductor structure comprises at least one conductor that extends horizontally at least partially within the magnetic core. The conductor extends in the z-direction within the magnetic core between the first conductor layer and the second conductor layer. One or more vias extend within the dielectric adjacent to the magnetic core between the first conductor layer and the second conductor layer. The conductor of the inductor has a length extending through the magnetic core that is greater than a width of the conductor.

公开(公告)号：US20200020652A1

公开(公告)日：2020-01-16

申请号：US16035129

申请日：2018-07-13

Applicant: Intel Corporation

Inventor： Michael J. Hill ,  Anne Augustine ,  Huong Do ,  William Lambert

IPC: H01L23/64 ,  H01L23/32 ,  H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Embodiments include a microelectronic device package structure having an inductor at least partially embedded within a substrate. At least one thermal solution structure may be on a surface of the inductor, and may be thermally coupled with the inductor. The one or more thermal solution structures provide a thermal pathway for cooling for the inductor, and extend a thermal time constant of the inductor.