公开(公告)号：WO2018182595A1

公开(公告)日：2018-10-04

申请号：PCT/US2017/024780

申请日：2017-03-29

Applicant: INTEL CORPORATION

Inventor： PIETAMBARAM, Srinivas V. ,  MANEPALLI, Rahul N. ,  AKKINEPALLY, Praneeth ,  JONES, Jesse C. ,  KANAOKA, Yosuke ,  SENEVIRATNE, Dilan

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/67

Abstract: Described are microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.

公开(公告)号：EP4546420A1

公开(公告)日：2025-04-30

申请号：EP24196789.2

申请日：2024-08-27

Applicant: INTEL Corporation

Inventor： DUAN, Gang ,  KANAOKA, Yosuke ,  LIU, Minglu ,  PIETAMBARAM, Srinivas V. ,  MARIN, Brandon C. ,  SHAN, Bohan ,  CHEN, Haobo ,  ECTON, Jeremy ,  DUONG, Benjamin T. ,  NAD, Suddhasattwa

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer having first dies in a first insulating material; a second layer on the first layer, the second layer including second dies having a first thickness and third dies having a second thickness different than the first thickness, the second dies and the third dies in a second insulating material, wherein the second dies and third dies have a first surface and an opposing second surface, and wherein the first surfaces of the second and third dies have a combined surface area between 3,000 square millimeters (mm 2 ) and 9,000 mm 2 ; and a redistribution layer (RDL) between the first layer and the second layer, the RDL including conductive pathways, wherein the first dies are electrically coupled to the second dies and the third dies by the conductive pathways and by interconnects.

公开(公告)号：EP4148784A1

公开(公告)日：2023-03-15

申请号：EP22189707.7

申请日：2022-08-10

Applicant: INTEL Corporation

Inventor： MCREE, Robin ,  KANAOKA, Yosuke ,  DUAN, Gang ,  LIU, Jinhe ,  GOSSELIN, Timothy A.

IPC: H01L23/538

Abstract: Disclosed herein are embedded heterogeneous architectures having minimized die shift and methods for manufacturing the same. The architectures may include a substrate, a bridge, and a material attached to the substrate. The substrate may include a first subset of vias and a second subset of vias. The bridge may be located in between the first subset and the second subset of vias. The material may include a first portion located proximate the first subset of vias, and a second portion located proximate the second subset of vias. The first and second portions may define a partial boundary of a cavity formed within the substrate and the bridge may be located within the cavity.