公开(公告)号：WO1998029816A1

公开(公告)日：1998-07-09

申请号：PCT/US1997018425

申请日：1997-10-14

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  PASHLEY, Richard, D. ,  WINSTON, Mark, D. ,  JUNGROTH, Owen, W. ,  KAPLAN, David, J.

IPC: G06F13/00

CPC classification number: G11C11/005

Abstract: An integrated circuit (IC) memory device (100) and method for interfacing volatile and non volatile memory arrays formed on a single semiconductor substrate. Data to be written from an external device such as a processor (104) is initially written to a volatile random access memory (RAM) write buffer array (101), and then written from the volatile RAM array (101) to a nonvolatile flash array (103) via an interface (102) to provide nonvolatile data storage at speeds typical of a RAM device. Data from first and second block addresses in the arrays may be merged in a flash merge buffer, and validity bits may be used to ensure data coherency. Data may be simultaneously written to or read from the volatile RAM array (101) during a time in which data is being read from or written to the nonvolatile flash array (103), which may be an EPROM or EEPROM.

Abstract translation: 一种集成电路（IC）存储器件（100）以及用于对形成在单个半导体衬底上的易失性和非易失性存储器阵列进行接口的方法。 要从诸如处理器（104）的外部设备写入的数据被初始写入到易失性随机存取存储器（RAM）写入缓冲器阵列（101）中，然后从易失性RAM阵列（101）写入非易失性闪存阵列 （103）经由接口（102），以在RAM设备的典型速度下提供非易失性数据存储。 阵列中的第一和第二块地址的数据可以合并在闪存合并缓冲器中，并且可以使用有效位来确保数据一致性。 在数据被读取或写入非易失性闪存阵列（103）的时间期间，数据可以被同时写入到易失性RAM阵列（101）或从易失性RAM阵列读取，所述非易失性闪存阵列（103）可以是EPROM或EEPROM。

公开(公告)号：EP0974097A1

公开(公告)日：2000-01-26

申请号：EP97910079.9

申请日：1997-10-14

Applicant: INTEL CORPORATION

Inventor： PASHLEY, Richard, D. ,  WINSTON, Mark, D. ,  JUNGROTH, Owen, W. ,  KAPLAN, David, J.

IPC: G06F13/00 ,  G11C14/00 ,  G11C16/06

CPC classification number: G11C11/005

Abstract: An integrated circuit (IC) memory device (100) and method for interfacing volatile and non volatile memory arrays formed on a single semiconductor substrate. Data to be written from an external device such as a processor (104) is initially written to a volatile random access memory (RAM) write buffer array (101), and then written from the volatile RAM array (101) to a nonvolatile flash array (103) via an interface (102) to provide nonvolatile data storage at speeds typical of a RAM device. Data from first and second block addresses in the arrays may be merged in a flash merge buffer, and validity bits may be used to ensure data coherency. Data may be simultaneously written to or read from the volatile RAM array (101) during a time in which data is being read from or written to the nonvolatile flash array (103), which may be an EPROM or EEPROM.