公开(公告)号：WO2020190369A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/014766

申请日：2020-01-23

Applicant: INTEL CORPORATION

Inventor： MATAM, Naveen ,  CHENEY, Lance ,  FINLEY, Eric ,  GEORGE, Varghese ,  JAHAGIRDAR, Sanjeev ,  KOKER, Altug ,  MASTRONARDE, Josh ,  RAJWANI, Iqbal ,  STRIRAMASSARMA, Lakshminarayanan ,  TESHOME, Melaku ,  VEMULAPALLI, Vikranth ,  XAVIER, Binoj

IPC: G06F13/40 ,  H01L25/11

Abstract: Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

公开(公告)号：WO2020190370A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/014770

申请日：2020-01-23

Applicant: INTEL CORPORATION

Inventor： KOKER, Altug ,  CHENEY, Lance ,  FINLEY, Eric ,  GEORGE, Varghese ,  JAHAGIRDAR, Sanjeev ,  MASTRONARDE, Josh ,  MATAM, Naveen ,  RAJWANI, Iqbal ,  STRIRAMASSARMA, Lakshminarayanan ,  TESHOME, Melaku ,  VEMULAPALLI, Vikranth ,  XAVIER, Binoj

IPC: G06T1/20

Abstract: A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the onboard logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets. With such an interchangeable design, higher or lower density memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.

公开(公告)号：EP3938995A1

公开(公告)日：2022-01-19

申请号：EP20706080.7

申请日：2020-01-23

Applicant: INTEL Corporation

Inventor： KOKER, Altug ,  CHENEY, Lance ,  FINLEY, Eric ,  GEORGE, Varghese ,  JAHAGIRDAR, Sanjeev ,  MASTRONARDE, Josh ,  MATAM, Naveen ,  RAJWANI, Iqbal ,  STRIRAMASSARMA, Lakshminarayanan ,  TESHOME, Melaku ,  VEMULAPALLI, Vikranth ,  XAVIER, Binoj

IPC: G06T1/20

公开(公告)号：EP3938918A1

公开(公告)日：2022-01-19

申请号：EP20709367.5

申请日：2020-01-23

Applicant: INTEL Corporation

Inventor： MATAM, Naveen ,  CHENEY, Lance ,  FINLEY, Eric ,  GEORGE, Varghese ,  JAHAGIRDAR, Sanjeev ,  KOKER, Altug ,  MASTRONARDE, Josh ,  RAJWANI, Iqbal ,  STRIRAMASSARMA, Lakshminarayanan ,  TESHOME, Melaku ,  VEMULAPALLI, Vikranth ,  XAVIER, Binoj

IPC: G06F13/40 ,  H01L25/11