公开(公告)号：WO2016105783A1

公开(公告)日：2016-06-30

申请号：PCT/US2015/062220

申请日：2015-11-23

Applicant: INTEL CORPORATION

Inventor： TEOH, Ee Loon ,  OOI, Eng Hun ,  MOZAK, Christopher P. ,  MCFARLANE, Brian R.

IPC: H03M13/00

CPC classification number: G06F13/4282 ,  G06F13/1668 ,  G06F13/28 ,  G06F21/79 ,  Y02D10/14 ,  Y02D10/151

Abstract: An I/O interface supports scrambling, where the scrambling can include nonlinear scrambling of the scrambling code, or dynamic bus inversion of the scrambling code, or selective switching of selected bits of the scrambling code, or a combination of these. The transmitting device includes a scrambler and the receiving device includes a descrambler. Both the scrambler and the descrambler generate a linear feedback scrambling code modified by applying one or more of the techniques mentioned above. The modified scrambling code may cause fewer than half of the scrambled output bits to be toggled with respect to a previous scrambled output. The scrambler applies the modified scrambling code to a signal to transmit. The descrambler applies the modified scrambling code to a received signal.

Abstract translation: I / O接口支持加扰，其中加扰可以包括扰码的非线性加扰或扰码的动态总线反转，或扰码的选定位的选择性切换，或这些的组合。 发送设备包括加扰器，并且接收设备包括解扰器。 加扰器和解扰器都产生通过应用上述一种或多种技术修改的线性反馈扰码。 经修改的扰码可能导致少于一半的加扰输出比特相对于先前的加扰输出被切换。 扰频器将修改的扰码应用于要发送的信号。 解扰器将修改的扰码应用于接收信号。

公开(公告)号：WO2017054002A1

公开(公告)日：2017-03-30

申请号：PCT/US2016/053839

申请日：2016-09-26

Applicant: INTEL CORPORATION

Inventor： KHAN, Jawad B. ,  WEBB, Randall K. ,  GREEN, Kelvin D. ,  MCFARLANE, Brian R.

IPC: G06F13/42 ,  G06F13/16 ,  G06F15/76

CPC classification number: G06F13/1668 ,  G06F13/102 ,  G06F13/4068 ,  G06F13/4282

Abstract: Examples may include techniques to couple with a storage device via multiple communication ports. A first communication port at the storage device may be configurable to couple with at least one other storage device, a field programmable gate array (FPGA)/programmable logic or application-specific integrated circuit (ASIC) via a serial communication link. A second communication port at the storage device is arranged to couple with a host computing device.

Abstract translation: 示例可以包括经由多个通信端口与存储设备耦合的技术。 存储设备上的第一通信端口可以被配置为经由串行通信链路与至少一个其他存储设备，现场可编程门阵列（FPGA）/可编程逻辑或专用集成电路（ASIC）耦合。 存储设备处的第二通信端口被布置成与主计算设备耦合。

公开(公告)号：EP3238345A1

公开(公告)日：2017-11-01

申请号：EP15873988.8

申请日：2015-11-23

Applicant: Intel Corporation

Inventor： TEOH, Ee Loon ,  OOI, Eng Hun ,  MOZAK, Christopher P. ,  MCFARLANE, Brian R.

IPC: H03M13/00

CPC classification number: G06F13/4282 ,  G06F13/1668 ,  G06F13/28 ,  G06F21/79 ,  Y02D10/14 ,  Y02D10/151

Abstract: An I/O interface supports scrambling, where the scrambling can include nonlinear scrambling of the scrambling code, or dynamic bus inversion of the scrambling code, or selective switching of selected bits of the scrambling code, or a combination of these. The transmitting device includes a scrambler and the receiving device includes a descrambler. Both the scrambler and the descrambler generate a linear feedback scrambling code modified by applying one or more of the techniques mentioned above. The modified scrambling code may cause fewer than half of the scrambled output bits to be toggled with respect to a previous scrambled output. The scrambler applies the modified scrambling code to a signal to transmit. The descrambler applies the modified scrambling code to a received signal.

Abstract translation: I / O接口支持加扰，其中加扰可以包括加扰码的非线性加扰，或加扰码的动态总线倒置，或加扰码的选定位的选择性切换，或这些的组合。 发送设备包括扰码器，并且接收设备包括解扰器。 扰码器和解扰器都生成通过应用上述一种或多种技术而修改的线性反馈扰码。 修改的扰码可以使得相对于先前的扰码输出来说，少于一半的扰码输出位被切换。 扰码器将修改的扰码应用于要发送的信号。 解扰器将修改的扰码应用于接收的信号。