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    LOWER-POWER SCRAMBLING WITH IMPROVED SIGNAL INTEGRITY
    1.
    发明申请
    LOWER-POWER SCRAMBLING WITH IMPROVED SIGNAL INTEGRITY 审中-公开
    具有改进的信号完整性的下功率SCRAMBLING

    公开(公告)号：WO2016105783A1

    公开(公告)日：2016-06-30

    申请号：PCT/US2015/062220

    申请日：2015-11-23

    Applicant: INTEL CORPORATION

    Inventor： TEOH, Ee Loon ,  OOI, Eng Hun ,  MOZAK, Christopher P. ,  MCFARLANE, Brian R.

    IPC: H03M13/00

    CPC classification number: G06F13/4282 ,  G06F13/1668 ,  G06F13/28 ,  G06F21/79 ,  Y02D10/14 ,  Y02D10/151

    Abstract: An I/O interface supports scrambling, where the scrambling can include nonlinear scrambling of the scrambling code, or dynamic bus inversion of the scrambling code, or selective switching of selected bits of the scrambling code, or a combination of these. The transmitting device includes a scrambler and the receiving device includes a descrambler. Both the scrambler and the descrambler generate a linear feedback scrambling code modified by applying one or more of the techniques mentioned above. The modified scrambling code may cause fewer than half of the scrambled output bits to be toggled with respect to a previous scrambled output. The scrambler applies the modified scrambling code to a signal to transmit. The descrambler applies the modified scrambling code to a received signal.

    Abstract translation: I / O接口支持加扰，其中加扰可以包括扰码的非线性加扰或扰码的动态总线反转，或扰码的选定位的选择性切换，或这些的组合。 发送设备包括加扰器，并且接收设备包括解扰器。 加扰器和解扰器都产生通过应用上述一种或多种技术修改的线性反馈扰码。 经修改的扰码可能导致少于一半的加扰输出比特相对于先前的加扰输出被切换。 扰频器将修改的扰码应用于要发送的信号。 解扰器将修改的扰码应用于接收信号。

    EFFICIENT LOW POWER EXIT SEQUENCE FOR PERIPHERAL DEVICES
    3.
    发明申请
    EFFICIENT LOW POWER EXIT SEQUENCE FOR PERIPHERAL DEVICES 审中-公开
    对外围设备有效的低功率输出序列

    公开(公告)号：WO2014051722A1

    公开(公告)日：2014-04-03

    申请号：PCT/US2013/045018

    申请日：2013-06-10

    Applicant: INTEL CORPORATION

    Inventor： OOI, Eng Hun

    IPC: G06F1/32 ,  G06F13/00

    CPC classification number: G06F1/3206 ,  G06F1/325 ,  G06F1/3268 ,  Y02D10/154 ,  Y02D50/20

    Abstract: Embodiments of the invention describe methods, apparatuses and systems for providing an efficient low power exit sequence for peripheral devices. In embodiments of the invention, a signal from a host device is transmitted to a SATA peripheral device for exiting a low-power state. An initialization time for OOB transmission and reception logic of the SATA peripheral device is tracked, and a reference time value based on the tracked initialization time is stored. In subsequent transitions from said low-power state, the reference time value for waking a host physical layer is utilized, thereby improving the efficiency of the management and use of said low power state. In some embodiments, the above described tracked initialization comprises a time from a transmission of an OOB signal (from the host to the peripheral device) to receiving an OOB response at the host device from the SATA peripheral device.

    Abstract translation: 本发明的实施例描述了用于为外围设备提供有效的低功率出口序列的方法，装置和系统。 在本发明的实施例中，来自主机设备的信号被传送到SATA外围设备以退出低功率状态。 跟踪SATA外围设备的OOB发送和接收逻辑的初始化时间，并且存储基于追踪的初始化时间的基准时间值。 在从所述低功率状态的后续转换中，利用用于唤醒主机物理层的参考时间值，从而提高所述低功率状态的管理和使用的效率。 在一些实施例中，上述跟踪的初始化包括从OOB信号（从主机到外围设备）的传输到在主机设备处从SATA外围设备接收OOB响应的时间。

    GATHERING SENSED DATA FROM DEVICES TO MANAGE HOST COMMAND TRANSMISSION AND COOLING OF THE DEVICES
    4.
    发明申请
    GATHERING SENSED DATA FROM DEVICES TO MANAGE HOST COMMAND TRANSMISSION AND COOLING OF THE DEVICES 审中-公开
    从设备获取感知数据以管理设备的命令传输和冷却

    公开(公告)号：WO2016186793A1

    公开(公告)日：2016-11-24

    申请号：PCT/US2016/028707

    申请日：2016-04-21

    Applicant: INTEL CORPORATION

    Inventor： RANGARAJAN, Thanunathan ,  OOI, Eng Hun ,  RANGARAJAN, Madhusudhan ,  CONE, Robert W. ,  AHUJA, Nishi

    IPC: G06F1/20 ,  G06F3/06 ,  G06F9/30

    CPC classification number: G06F3/061 ,  G06F1/206 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0689

    Abstract: Provided are a computer readable storage media, method, and system for gathering sensed data from devices to manage host command transmission and cooling of the device. Host commands are retrieved from a host memory in a host to perform Input/Output operations with respect to a device. The retrieved host commands are transmitted to the device to perform the I/O operations of the host command. A monitor command is transmitted to obtain sensed data from the device while processing the host commands. A rate of transmitting the host commands is adjusted in response to determining that the sensed data received from the device in response to the monitor command satisfies a condition.

    Abstract translation: 提供了一种用于从设备收集感测数据以管理主机命令传输和冷却设备的计算机可读存储介质，方法和系统。 从主机中的主机存储器检索主机命令，以对设备执行输入/输出操作。 检索到的主机命令被发送到设备以执行主机命令的I / O操作。 发送监视命令以在处理主机命令时从设备获得感测数据。 响应于确定响应于监视命令从设备接收到的感测数据满足条件，调整发送主机命令的速率。

    MEMORY LATENCY MANAGEMENT
    5.
    发明申请
    MEMORY LATENCY MANAGEMENT 审中-公开
    内存管理

    公开(公告)号：WO2014163880A1

    公开(公告)日：2014-10-09

    申请号：PCT/US2014/018513

    申请日：2014-02-26

    Applicant: INTEL CORPORATION ,  ROYER, JR., Robert J. ,  FANNING, Blaise ,  OOI, Eng Hun

    Inventor： ROYER, JR., Robert J. ,  FANNING, Blaise ,  OOI, Eng Hun

    IPC: G06F13/14 ,  G06F12/00 ,  G06F11/10

    CPC classification number: G06F11/1064 ,  G06F11/1048 ,  G06F12/084 ,  G06F12/0866 ,  G06F2212/1032 ,  G06F2212/313

    Abstract: Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator associated with the data, and implement a data management policy in response to the error correction code indicator. Other embodiments are also disclosed and claimed.

    Abstract translation: 描述了用于管理存储器延迟操作的装置，系统和方法。 在一个实施例中，电子设备包括处理器和用于从远程存储器设备接收数据的存储器控​​制逻辑，将数据存储在本地高速缓冲存储器中，接收与该数据相关联的纠错码指示符，并实现数据管理策略 响应于纠错码指示器。 还公开并要求保护其他实施例。

    SERIAL STORAGE PROTOCOL COMPATIBLE FRAME CONVERSION, AT LEAST IN PART
    6.
    发明申请
    SERIAL STORAGE PROTOCOL COMPATIBLE FRAME CONVERSION, AT LEAST IN PART 审中-公开
    串行存储协议兼容性帧转换，至少部分

    公开(公告)号：WO2014055139A1

    公开(公告)日：2014-04-10

    申请号：PCT/US2013/046106

    申请日：2013-06-17

    Applicant: INTEL CORPORATION ,  GUOK, Ngek Leong ,  GAN, Chai Huat ,  OOI, Eng Hun

    Inventor： GUOK, Ngek Leong ,  GAN, Chai Huat ,  OOI, Eng Hun

    IPC: G06F3/00 ,  G06F13/12

    CPC classification number: G06F3/0661 ,  G06F3/0607 ,  G06F3/0613 ,  G06F3/0673 ,  G06F3/0676

    Abstract: An embodiment may include circuitry to (a) convert, at least in part, at least one serial storage protocol compatible frame into at least one packet that is compatible, at least in part, with a multi-lane input/output (I/O) protocol, and/or (b) convert, at least in part, the at least one packet into the at least one frame. The at least one packet may be transmitted via a physical layer that is compatible, at least in part, with the multi-lane I/O protocol. The at least one packet may comprise frame information structure (FIS) information of the at least one frame.

    Abstract translation: 一个实施例可以包括以下电路：（a）至少部分地将至少一个串行存储协议兼容帧转换成至少一个分组，至少部分地与多通道输入/输出（I / O ）协议，和/或（b）至少部分地将所述至少一个分组转换成所述至少一个帧。 至少一个分组可以经由至少部分地与多通道I / O协议兼容的物理层来传输。 所述至少一个分组可以包括所述至少一个帧的帧信息结构（FIS）信息。

    IN-SYSTEM PROVISIONING OF FIRMWARE FOR A HARDWARE PLATFORM
    8.
    发明申请
    IN-SYSTEM PROVISIONING OF FIRMWARE FOR A HARDWARE PLATFORM 审中-公开
    硬件平台固件的系统内提供

    公开(公告)号：WO2015149020A1

    公开(公告)日：2015-10-01

    申请号：PCT/US2015/023175

    申请日：2015-03-27

    Applicant: INTEL CORPORATION

    Inventor： SARANGDHAR, Nitin ,  ROYER, Robert, Jr. ,  OOI, Eng Hun ,  MCFARLANE, Brian ,  KATARIA, Mukesh

    IPC: G06F9/44 ,  G06F21/62

    CPC classification number: G06F21/572 ,  G06F9/4403 ,  G06F9/4406 ,  G06F9/4411 ,  G06F11/1417 ,  G06F12/1408 ,  G06F21/57 ,  G06F21/575 ,  G06F2212/1052 ,  G06F2221/03 ,  G06F2221/033 ,  H04L63/0435

    Abstract: A hardware platform includes a nonvolatile storage device that can store system firmware as well as code for the primary operating system for the hardware platform. The hardware platform includes a controller that determines the hardware platform lacks functional firmware to boot the primary operating system from the storage device. The controller accesses a firmware image from an external interface that interfaces a device external to the hardware platform, where the external device is a firmware image source. The controller provisions the firmware from the external device to the storage device and initiates a boot sequence from the provisioned firmware.

    Abstract translation: 硬件平台包括可以存储系统固件的非易失性存储设备以及用于硬件平台的主操作系统的代码。 硬件平台包括一个确定硬件平台的控制器缺乏从存储设备引导主操作系统的功能固件。 控制器从外部接口访问固件映像，该外部接口将硬件平台外部的设备连接到外部设备是固件映像源。 控制器将固件从外部设备提供给存储设备，并从配置的固件启动启动顺序。

    A METHOD AND APPARATUS FOR USING ADVANCED HOST CONTROLLER INTERFACE TO TRANSFER DATA
    9.
    发明申请
    A METHOD AND APPARATUS FOR USING ADVANCED HOST CONTROLLER INTERFACE TO TRANSFER DATA 审中-公开
    一种使用高级主机控制器接口传输数据的方法和装置

    公开(公告)号：WO2006036572A2

    公开(公告)日：2006-04-06

    申请号：PCT/US2005/032933

    申请日：2005-09-13

    Applicant: INTEL CORPORATION ,  OOI, Eng Hun

    Inventor： OOI, Eng Hun

    IPC: G06F13/38

    CPC classification number: G06F13/385

    Abstract: A method and apparatus for entering a mode of a host controller and omitting a state of a state machine sequence of the host controller for data exchange by the host controller are disclosed. For one embodiment, the method and apparatus include setting a bit before a command information is transmitted to a separate device and exchanging data without sending the command information to the separate device. The bit of the embodiment indicates a current task file status.

    Abstract translation: 公开了一种用于进入主机控制器的模式并省略由主机控制器进行数据交换的主机控制器的状态机序列的状态的方法和装置。 对于一个实施例，所述方法和装置包括在将命令信息发送到单独的设备之前设置位，并且在不向所述单独设备发送命令信息的情况下交换数据。 该实施例的位指示当前任务文件状态。

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