公开(公告)号：WO1996002916A1

公开(公告)日：1996-02-01

申请号：PCT/US1995007745

申请日：1995-06-16

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  ROSEN, Eitan ,  MILSTAIN, Yakov

IPC: G11C13/00

CPC classification number: G11C29/50016 ,  G11C11/41 ,  G11C29/50

Abstract: A memory circuit (20) is disclosed with stress circuitry for detecting data retention defects in the memory cells. The memory circuit (20) comprises a memory cell array (22) coupled to bit lines, an access circuit (24) coupled to access the memory cells, and a discharge circuit coupled to stress the memory cells.

Abstract translation: 公开了一种用于检测存储器单元中的数据保持缺陷的应力电路的存储器电路（20）。 存储器电路（20）包括耦合到位线的存储单元阵列（22），耦合到存取单元的存取电路（24），以及耦合以压缩存储单元的放电电路。

公开(公告)号：EP0782747B1

公开(公告)日：2000-08-16

申请号：EP95923957.5

申请日：1995-06-16

Applicant: INTEL CORPORATION

Inventor： ROSEN, Eitan ,  MILSTAIN, Yakov

IPC: G11C13/00 ,  G11C29/00

CPC classification number: G11C29/50016 ,  G11C11/41 ,  G11C29/50

Abstract: A memory circuit (20) is disclosed with stress circuitry for detecting data retention defects in the memory cells. The memory circuit (20) comprises a memory cell array (22) coupled to bit lines, an access circuit (24) coupled to access the memory cells, and a discharge circuit coupled to stress the memory cells.

公开(公告)号：EP0782747A1

公开(公告)日：1997-07-09

申请号：EP95923957.0

申请日：1995-06-16

Applicant: INTEL CORPORATION

Inventor： ROSEN, Eitan ,  MILSTAIN, Yakov

IPC: G01R31 ,  G11C11 ,  G11C29

CPC classification number: G11C29/50016 ,  G11C11/41 ,  G11C29/50

Abstract: A memory circuit (20) is disclosed with stress circuitry for detecting data retention defects in the memory cells. The memory circuit (20) comprises a memory cell array (22) coupled to bit lines, an access circuit (24) coupled to access the memory cells, and a discharge circuit coupled to stress the memory cells.