公开(公告)号：WO2003003377A3

公开(公告)日：2003-01-09

申请号：PCT/US2002/020644

申请日：2002-06-28

Applicant: INTEL CORPORATION

Inventor： ISENBERGER, Mark ,  MU, Xiao-Chun ,  LI, Jian

IPC: G11C11/22

Abstract: One embodiment of the invention relates to a polymer memory device and a method of making it. The polymer memory device may include a composite or single layer of a ferroelectric polymer memory that addresses surface engineering needs according to various embodiments. The ferroelectric polymer memory structure may include crystalline ferroelectric polymer layers such as single and co-polymer compositions, The structure may include spin-on and/or Langmuir- Blodgett deposited compositions. One embodiment of the invention relates to a method making embodiments of the polymer memory device. One embodiment of the invention relates to a memory system that allows the polymer memory device to interface with various existing hosts.

公开(公告)号：WO2002015266A3

公开(公告)日：2002-02-21

申请号：PCT/US2001/025060

申请日：2001-08-10

Applicant: INTEL CORPORATION

Inventor： MU, Xiao-Chun ,  MA, Qing ,  FUJIMOTO, Harry

IPC: H01L23/31

Abstract: A microelectronic package including a microelectronic die having an active surface and at least one side. An encapsulation material is disposed adjacent the microelectronic die side(s), wherein the encapsulation material includes at least one surface substantially planar to the microelectronic die active surface. A first dielectric material layer may be disposed on at least a portion of the microelectronic die active surface and the encapsulation material surface. At least one conductive trace is then disposed on the first dielectric material layer. The conductive trace(s) is in electrical contact with the microelectronic die active surface. At least one conductive trace extends adjacent the microelectronic die active surface and adjacent the encapsulation material surface.

公开(公告)号：WO2003003377A2

公开(公告)日：2003-01-09

申请号：PCT/US2002/020644

申请日：2002-06-28

Applicant: INTEL CORPORATION

Inventor： ISENBERGER, Mark ,  MU, Xiao-Chun ,  LI, Jian

IPC: G11C11/22

CPC classification number: H01L27/11502 ,  H01L21/28291 ,  H01L29/516

Abstract: One embodiment of the invention relates to a polymer memory device and a method of making it. The polymer memory device may include a composite or single layer of a ferroelectric polymer memory that addresses surface engineering needs according to various embodiments. The ferroelectric polymer memory structure may include crystalline ferroelectric polymer layers such as single and co-polymer compositions, The structure may include spin-on and/or Langmuir- Blodgett deposited compositions. One embodiment of the invention relates to a method making embodiments of the polymer memory device. One embodiment of the invention relates to a memory system that allows the polymer memory device to interface with various existing hosts.

Abstract translation: 本发明的一个实施方案涉及聚合物记忆装置及其制备方法。 聚合物存储器件可以包括根据各种实施例的满足表面工程需要的铁电聚合物存储器的复合层或单层。 铁电聚合物记忆结构可以包括结晶铁电聚合物层，例如单一和共聚物组合物。该结构可以包括旋涂和/或Langmuir-Blodgett沉积的组合物。 本发明的一个实施方案涉及制备聚合物存储器件的实施方案的方法。 本发明的一个实施例涉及允许聚合物存储器件与各种现有主机接口的存储器系统。

公开(公告)号：EP1354351A2

公开(公告)日：2003-10-22

申请号：EP01962043.4

申请日：2001-08-10

Applicant: INTEL CORPORATION

Inventor： MU, Xiao-Chun ,  MA, Qing ,  FUJIMOTO, Harry

IPC: H01L23/31

CPC classification number: H01L21/568 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/4334 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/351 ,  H05K1/185 ,  H05K3/4602 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00

Abstract: A microelectronic package including a microelectronic die having an active surface and at least one side. An encapsulation material is disposed adjacent the microelectronic die side(s), wherein the encapsulation material includes at least one surface substantially planar to the microelectronic die active surface. A first dielectric material layer may be disposed on at least a portion of the microelectronic die active surface and the encapsulation material surface. At least one conductive trace is then disposed on the first dielectric material layer. The conductive trace(s) is in electrical contact with the microelectronic die active surface. At least one conductive trace extends adjacent the microelectronic die active surface and adjacent the encapsulation material surface.

公开(公告)号：EP1354351B1

公开(公告)日：2009-04-15

申请号：EP01962043.4

申请日：2001-08-10

Applicant: Intel Corporation

Inventor： MU, Xiao-Chun ,  MA, Qing ,  FUJIMOTO, Harry

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/60 ,  H01L23/538

CPC classification number: H01L21/568 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/4334 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/351 ,  H05K1/185 ,  H05K3/4602 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00

Abstract: A microelectronic package including a microelectronic die having an active surface and at least one side. An encapsulation material is disposed adjacent the microelectronic die side(s), wherein the encapsulation material includes at least one surface substantially planar to the microelectronic die active surface. A first dielectric material layer may be disposed on at least a portion of the microelectronic die active surface and the encapsulation material surface. At least one conductive trace is then disposed on the first dielectric material layer. The conductive trace(s) is in electrical contact with the microelectronic die active surface. At least one conductive trace extends adjacent the microelectronic die active surface and adjacent the encapsulation material surface.

公开(公告)号：EP1354354A2

公开(公告)日：2003-10-22

申请号：EP01992286.3

申请日：2001-11-09

Applicant: INTEL CORPORATION

Inventor： HENAO, Maria, V. ,  MU, Xiao-Chun ,  MA, Qing ,  VU, Quat, T. ,  TOWLE, Steven, N.

IPC: H01L23/433 ,  H01L23/538

CPC classification number: H01L24/20 ,  H01L21/561 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/82 ,  H01L2924/00

Abstract: A microelectronic package fabrication technology that attaches at least one microelectronic die onto a heat spreader and encepsulates the microelectronic die/dice thereon which may further include a microelectronic packaging core abutting the heat spreader wherein the microelectronic die/dice reside within at least one opening in a microelectronic package core. After encapsulation, build-up layers may be fabricated to form electrical connections with the microelectronic die/dice.

公开(公告)号：EP1356519B1

公开(公告)日：2014-04-30

申请号：EP01968251.7

申请日：2001-08-29

Applicant: Intel Corporation

Inventor： HENAO, Maria ,  MU, Xiao-Chun ,  MA, Qing ,  VU, Quat ,  LI, Jian

IPC: H01L23/532 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L24/19 ,  H01L21/568 ,  H01L23/532 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19041 ,  Y10T29/4935 ,  H01L2224/96 ,  H01L2224/82 ,  H01L2924/00

公开(公告)号：EP1356519A2

公开(公告)日：2003-10-29

申请号：EP01968251.7

申请日：2001-08-29

Applicant: INTEL CORPORATION

Inventor： HENAO, Maria ,  MU, Xiao-Chun ,  MA, Qing ,  VU, Quat ,  LI, Jian

IPC: H01L23/538

CPC classification number: H01L24/19 ,  H01L21/568 ,  H01L23/532 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19041 ,  Y10T29/4935 ,  H01L2224/96 ,  H01L2224/82 ,  H01L2924/00

Abstract: A microelectronic package including a microelectronic die disposed within an opening in a microelectronic packaging core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic die. Build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die, the encapsulant material, and the microelectronic package core to form the microelectronic package.