公开(公告)号：US12074514B2

公开(公告)日：2024-08-27

申请号：US17025745

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Kaladhar Radhakrishnan ,  Beomseok Choi ,  Michael Hill

IPC: H02M3/07 ,  H01L23/00 ,  H01L25/065 ,  H02M1/00

CPC classification number: H02M3/07 ,  H01L24/17 ,  H01L25/0655 ,  H01L2924/1427 ,  H02M1/0045 ,  H02M1/009

Abstract: Embodiments disclosed herein include two stage voltage regulators for electronic systems. In an embodiment, a voltage regulator comprises a switched capacitor voltage regulator (SCVR). In an embodiment, the SCVR receives a first voltage as an input and outputs a plurality of SCVR output voltages. In an embodiment, the voltage regulator further comprises a low-dropout (LDO) regulator. In an embodiment, the LDO regulator receives one or more of the plurality of SCVR output voltages as LDO input voltages, and where the LDO regulator outputs a second voltage.

公开(公告)号：US11380652B2

公开(公告)日：2022-07-05

申请号：US16635501

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Beomseok Choi ,  Kaladhar Radhakrishnan ,  William Lambert ,  Michael Hill ,  Krishna Bharath

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/522 ,  H01L25/00

Abstract: An apparatus is provided which comprises: a first set of one or more contacts on a first die surface, the first set of one or more contacts to couple with contacts of an integrated circuit die, one or more multi-level voltage clamps coupled with the first set of one or more contacts, the one or more multi-level voltage clamps switchable between two or more voltages, one or more integrated voltage regulators coupled with the one or more multi-level voltage clamps, the one or more integrated voltage regulators to provide an output voltage, one or more through silicon vias (TSVs) coupled with the one or more integrated voltage regulators, and a second set of one or more contacts on a second die surface, opposite the first die surface, the second set of one or more contacts coupled with the one or more TSVs, and the second set of one or more contacts to couple with contacts of a package substrate. Other embodiments are also disclosed and claimed.

公开(公告)号：US11215662B2

公开(公告)日：2022-01-04

申请号：US16020425

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： William Lambert ,  Kaladhar Radhakrishnan ,  Michael Hill

IPC: G01R31/28 ,  G05F1/46

Abstract: Techniques and mechanisms for mitigating damage to voltage regulator (VR) circuitry of a packaged device. In an embodiment, the VR circuitry comprises a circuit leg between a first node and a second node. During a burn-in process, the VR circuitry provides a regulated output voltage to a load circuit via the first node, wherein the output voltage is based on a supply voltage received via the second node. While the VR circuitry provides the regulated output voltage to the load circuit, a supply current is provided to the load circuit via a path which is independent of any leg which is between the first node and the second node. In another embodiment, an integrated circuit (IC) chip of the packaged device comprises the load circuit, and the leg further comprises an off-chip coil structure which is distinct from the IC chip.

公开(公告)号：US20200003829A1

公开(公告)日：2020-01-02

申请号：US16020425

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： William Lambert ,  Kaladhar Radhakrishnan ,  Michael Hill

IPC: G01R31/28 ,  G05F1/46

Abstract: Techniques and mechanisms for mitigating damage to voltage regulator (VR) circuitry of a packaged device. In an embodiment, the VR circuitry comprises a circuit leg between a first node and a second node. During a burn-in process, the VR circuitry provides a regulated output voltage to a load circuit via the first node, wherein the output voltage is based on a supply voltage received via the second node. While the VR circuitry provides the regulated output voltage to the load circuit, a supply current is provided to the load circuit via a path which is independent of any leg which is between the first node and the second node. In another embodiment, an integrated circuit (IC) chip of the packaged device comprises the load circuit, and the leg further comprises an off-chip coil structure which is distinct from the IC chip.

公开(公告)号：US20200251448A1

公开(公告)日：2020-08-06

申请号：US16635501

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Beomseok Choi ,  Kaladhar Radhakrishnan ,  William Lambert ,  Michael Hill ,  Krishna Bharath

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/522 ,  H01L25/00

Abstract: An apparatus is provided which comprises: a first set of one or more contacts on a first die surface, the first set of one or more contacts to couple with contacts of an integrated circuit die, one or more multi-level voltage clamps coupled with the first set of one or more contacts, the one or more multi-level voltage clamps switchable between two or more voltages, one or more integrated voltage regulators coupled with the one or more multi-level voltage clamps, the one or more integrated voltage regulators to provide an output voltage, one or more through silicon vias (TSVs) coupled with the one or more integrated voltage regulators, and a second set of one or more contacts on a second die surface, opposite the first die surface, the second set of one or more contacts coupled with the one or more TSVs, and the second set of one or more contacts to couple with contacts of a package substrate. Other embodiments are also disclosed and claimed.