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    DEVICE, SYSTEM AND METHOD FOR PROVIDING MEMS STRUCTURES OF A SEMICONDUCTOR PACKAGE
    1.
    发明申请
    DEVICE, SYSTEM AND METHOD FOR PROVIDING MEMS STRUCTURES OF A SEMICONDUCTOR PACKAGE 审中-公开
    用于提供半导体封装的MEMS结构的器件，系统和方法

    公开(公告)号：WO2015047257A1

    公开(公告)日：2015-04-02

    申请号：PCT/US2013/061762

    申请日：2013-09-25

    Applicant: INTEL CORPORATION ,  TEH, Weng Hong ,  IBRAHIM, Tarek A. ,  HANEY, Sarah K. ,  SOBIESKI, Daniel N. ,  ZANTYE, Parshuram B. ,  MAIR, Chad E. ,  KAMGAING, Telesphor

    Inventor： TEH, Weng Hong ,  IBRAHIM, Tarek A. ,  SOBIESKI, Daniel N. ,  ZANTYE, Parshuram B. ,  MAIR, Chad E. ,  KAMGAING, Telesphor

    IPC: H01L29/84

    CPC classification number: B81C1/00246 ,  B81B2201/0271 ,  B81C1/00261 ,  B81C1/00277 ,  H01L21/568 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/73267 ,  H01L2924/01079

    Abstract: Techniques and mechanisms for providing precisely fabricated structures of a semiconductor package. In an embodiment, a build-up carrier of the semiconductor package includes a layer of porous dielectric material. Seed copper and plated copper is disposed on the layer of porous dielectric material. Subsequent etching is performed to remove copper adjacent to the layer of porous dielectric material, forming a gap separating a suspended portion of a MEMS structure from the layer of porous dielectric material. In another embodiment, the semiconductor package includes a copper structure disposed between portions of an insulating layer or portions of a layer of silicon nitride material. The layer of silicon nitride material couples the insulating layer to another insulating layer. One or both of the insulating layers are each protected from desmear processing with a respective release layer structure.

    Abstract translation: 用于提供半导体封装的精确制造结构的技术和机构。 在一个实施例中，半导体封装的积聚载体包括多孔介电材料层。 种子铜和电镀铜设置在多孔电介质材料层上。 进行随后的蚀刻以去除邻近多孔介电材料层的铜，形成将MEMS结构的悬置部分与多孔介电材料层分开的间隙。 在另一个实施例中，半导体封装包括设置在绝缘层的一部分之间或者氮化硅材料层的一部分的铜结构。 氮化硅材料层将绝缘层耦合到另一绝缘层。 每个绝缘层中的一个或两个保护层不受去离子处理的剥离层结构的剥离。

    EMBEDDED BRIDGE ARCHITECTURE WITH THINNED SURFACE
    3.
    发明申请
    EMBEDDED BRIDGE ARCHITECTURE WITH THINNED SURFACE 审中-公开

    公开(公告)号：WO2022203788A1

    公开(公告)日：2022-09-29

    申请号：PCT/US2022/017022

    申请日：2022-02-18

    Applicant: INTEL CORPORATION

    Inventor： CHEN, Haobo ,  GUO, Xiaoying ,  FENG, Hongxia ,  DARMAWIKARTA, Kristof ,  NIE, Bai ,  IBRAHIM, Tarek A. ,  DUAN, Gang ,  ECTON, Jeremy D. ,  LI, Sheng C. ,  ARANA, Leonel

    IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

    Abstract: Embodiments disclosed herein include a multi-die packages with an embedded bridge and a thinned surface. In an example, a multi-die interconnect structure includes a package substrate having a cavity. A bridge die is in the cavity of the package substrate, the bridge die including silicon. A dielectric material is over the package substrate, over the bridge die, and in the cavity. A plurality of conductive bond pads is on the dielectric material. The multi-die interconnect structure further includes a plurality of conductive pillars, individual ones of the plurality of conductive pillars on a corresponding one of the plurality of conductive bond pads. A solder resist material is on the dielectric material, on exposed portions of the plurality of conductive bond pads, and laterally surrounding the plurality of conductive pillars. The plurality of conductive pillars has a top surface above a top surface of the solder resist material.

    MICROELECTRONIC STRUCTURES INCLUDING GLASS CORES
    4.
    发明申请
    MICROELECTRONIC STRUCTURES INCLUDING GLASS CORES 审中-公开

    公开(公告)号：WO2022132267A1

    公开(公告)日：2022-06-23

    申请号：PCT/US2021/051692

    申请日：2021-09-23

    Applicant: INTEL CORPORATION

    Inventor： PIETAMBARAM, Srinivas V. ,  IBRAHIM, Tarek A. ,  DUAN, Gang ,  VADLAMANI, Sai ,  PENMECHA, Bharat Prasad

    IPC: H01L23/538 ,  H01L23/14

    Abstract: Disclosed herein are microelectronic structures including glass cores, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a glass core having through-glass vias (TGVs) therein; a metallization region at a first face of the glass core, wherein a conductive pathway in the first metallization region is conductively coupled to at least one of the TGVs; a bridge component in the metallization region; a first conductive contact at a face of the metallization region, wherein the first conductive contact is conductively coupled to the conductive pathway; and a second conductive contact at the face of the metallization region, wherein the second conductive contact is conductively coupled to the bridge component.

    PACKAGE SUBSTRATE Z-DISAGGREGATION WITH LIQUID METAL INTERCONNECTS
    5.
    发明申请
    PACKAGE SUBSTRATE Z-DISAGGREGATION WITH LIQUID METAL INTERCONNECTS 审中-公开

    公开(公告)号：WO2022260732A1

    公开(公告)日：2022-12-15

    申请号：PCT/US2022/019193

    申请日：2022-03-07

    Applicant: INTEL CORPORATION

    Inventor： MARIN, Brandon Christian ,  IBRAHIM, Tarek A. ,  MEYYAPPAN, Karumbu Nathan ,  OUVAROV-BANCALERO, Valery ,  XU, Dingying

    IPC: H01L23/522 ,  H01L23/532 ,  H01L23/535 ,  H01L23/02 ,  H01L23/00 ,  H01L25/065

    Abstract: A z-disaggregated integrated circuit package substrate assembly comprises a first substrate component (a coreless patch), a second substrate component (a core patch), and a third substrate component (an interposer). The coreless patch comprises thinner dielectric layers and higher density routing and can comprise an embedded bridge to allow for communication between integrated circuit dies attached to the coreless patch. The core layer acts as a middle layer interconnect between the coreless patch and the interposer and comprises liquid metal interconnects to connect the core patch physically and electrically to the coreless patch and the interposer. Core patch through holes comprise liquid metal plugs. Some through holes can be surrounded by and coaxially aligned with magnetic plugs to provide improved power signal delivery. The interposer comprises thicker dielectric layers and lower density routing. The substrate assembly can reduce cost and provide improved overall yield and electrical performance relative to monolithic substrates.

    PHOTONIC INTEGRATED CIRCUIT PACKAGING ARCHITECTURE
    6.
    发明申请
    PHOTONIC INTEGRATED CIRCUIT PACKAGING ARCHITECTURE 审中-公开

    公开(公告)号：WO2022225633A1

    公开(公告)日：2022-10-27

    申请号：PCT/US2022/021314

    申请日：2022-03-22

    Applicant: INTEL CORPORATION

    Inventor： KARHADE, Omkar G. ,  LI, Xiaoqian ,  IBRAHIM, Tarek A. ,  MAHAJAN, Ravindranath Vithal ,  DESHPANDE, Nitin A.

    IPC: G02B6/43 ,  G02B6/42

    Abstract: Photonic packages and device assemblies that include photonic integrated circuits (PICs) coupled to optical lenses on lateral sides of the PICs. An example photonic package comprises a package support, an integrated circuit (IC), an insulating material, a PIC having an active side and a lateral side substantially perpendicular to the active side. At least one optical structure is on the active side. A substantial portion of the active side is in contact with the insulating material, and the PIC is electrically coupled to the package support and to the IC. The photonic package further includes an optical lens coupled to the PIC on the lateral side. In some embodiments, the photonic package further includes an interposer between the PIC or the IC and the package support.

    MICROELECTRONIC ASSEMBLIES WITH GLASS SUBSTRATES AND THIN FILM CAPACITORS
    9.
    发明公开
    MICROELECTRONIC ASSEMBLIES WITH GLASS SUBSTRATES AND THIN FILM CAPACITORS 审中-公开

    公开(公告)号：EP4199069A1

    公开(公告)日：2023-06-21

    申请号：EP22213169.0

    申请日：2022-12-13

    Applicant: INTEL Corporation

    Inventor： PIETAMBARAM, Srinivas V. ,  IBRAHIM, Tarek A. ,  MANEPALLI, Rahul N. ,  GUZEK, John ,  AZIMI, Hamid

    IPC: H01L23/15 ,  H01L23/13 ,  H01L23/538

    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a glass substrate, having a surface, including a through-glass-substrate via (TGV) and a cavity on the surface; a first die nested in the cavity; an insulating material on the surface of the glass substrate; a first conductive pillar and a second conductive pillar through the insulating material; a capacitor, in the insulating material, including a first conductive layer, on the surface of the glass substrate, electrically coupled to the TGV and the first conductive pillar forming a first plate of the capacitor, a dielectric layer on the first conductive layer; and a second conductive layer, on the dielectric layer, electrically coupled to the second conductive pillar forming a second plate of the capacitor; and a second die, on the insulating material, electrically coupled to the first die.

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