公开(公告)号：WO1998032063A2

公开(公告)日：1998-07-23

申请号：PCT/US1997022147

申请日：1997-12-03

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  JAYAKUMAR, Muthurajan ,  HUANG, Sunny, C. ,  MACWILLIAMS, Peter, D. ,  WU, William, S. ,  PAWLOWSKI, Stephen ,  PRASAD, Bindi, A.

IPC: G06F00/00

CPC classification number: G06F13/37 ,  G06F13/4252

Abstract: A split transaction bus in a computer system that permits out-of-order replies in a pipelined manner using an additional bus for use in the response phase.

Abstract translation: 计算机系统中的分流事务总线，其允许使用附加总线以流水线方式进行无序回复以用于响应阶段。

公开(公告)号：EP1046111B1

公开(公告)日：2004-05-06

申请号：EP99900759.4

申请日：1999-01-05

Applicant: INTEL CORPORATION

Inventor： MACWILLIAMS, Peter, D. ,  WU, William, S. ,  SAMPATH, Dilip, K. ,  PRASAD, Bindi, A.

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/385 ,  G06F13/4018 ,  G06F13/405

Abstract: A method and apparatus for transferring data between bus agents (102-105) in a computer system (100). The present invention includes transmitting a control signal (428, 426), from a first agent (102-105) to a second agent (102-105), via a first transfer protocol; and transmitting data (308) corresponding to the control signal (428, 426), from the first agent (102-105) to the second agent (102-105), via a second transfer protocol. In one embodiment, the control signals (428, 426) are transmitted from the first agent (102-105) to the second agent (102-105) via a synchronous transmission with respect to a bus clock (600); and, the data is transmitted via an asynchronous transmission with respect to the bus clock (600). The synchronous transmission is a common clock data transfer protocol, and the asynchronous transmission is a source clock data transfer protocol.

公开(公告)号：EP1046111A1

公开(公告)日：2000-10-25

申请号：EP99900759.4

申请日：1999-01-05

Applicant: INTEL CORPORATION

Inventor： MACWILLIAMS, Peter, D. ,  WU, William, S. ,  SAMPATH, Dilip, K. ,  PRASAD, Bindi, A.

IPC: G06F13/42

CPC classification number: G06F13/385 ,  G06F13/4018 ,  G06F13/405

Abstract: A method and apparatus for transferring data between bus agents (102-105) in a computer system (100). The present invention includes transmitting a control signal (428, 426), from a first agent (102-105) to a second agent (102-105), via a first transfer protocol; and transmitting data (308) corresponding to the control signal (428, 426), from the first agent (102-105) to the second agent (102-105), via a second transfer protocol. In one embodiment, the control signals (428, 426) are transmitted from the first agent (102-105) to the second agent (102-105) via a synchronous transmission with respect to a bus clock (600); and, the data is transmitted via an asynchronous transmission with respect to the bus clock (600). The synchronous transmission is a common clock data transfer protocol, and the asynchronous transmission is a source clock data transfer protocol.