公开(公告)号：WO1998029951A1

公开(公告)日：1998-07-09

申请号：PCT/US1997023939

申请日：1997-12-18

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  STAMOULIS, Georgios, I. ,  SUGISAWA, Junji ,  ZHANG, Michael, Y.

IPC: H03K19/0948

CPC classification number: H03K17/6872

Abstract: A low power data transmission circuit includes a pass gate (20) having parallel connected n and p-channel CMOS transistors that transmit input data (DATA). To reduce power in a first embodiment, a circuit (28) disables the parallel-connected p-channel pass gate transistor except when the input data is high (logical 1). The p-channel pass gate transistor is needed to pass logical 1's without degradation. In the first embodiment, the n-channel pass gate transistor is enabled to transmit the input data on every clock cycle (CLOCK). In a second embodiment, the circuit (30) disables the parallel-connected n-channel transistor except when the input data is low (logical 0). The n-channel pass gate transistor is needed to pass logical 0's without degradation. In this embodiment, the p-channel pass gate transistor is enabled to transmit the input data on every clock cycle. These transmission circuits achieve substantial power savings by avoiding unnecessary charging and discharging of the pass gate transistors' gate capacitance on every clock cycle.

Abstract translation: 低功率数据传输电路包括传输输入数据（DATA）的并行连接的n沟道CMOS晶体管和p沟道CMOS晶体管的栅极（20）。 为了在第一实施例中降低功率，除了输入数据高（逻辑1）之外，电路（28）禁用并联p沟道栅极晶体管。 需要p沟道栅极晶体管来使逻辑1不劣化。 在第一实施例中，n通道栅极晶体管能够在每个时钟周期（CLOCK）上传输输入数据。 在第二实施例中，除输入数据为低（逻辑0）之外，电路（30）禁止并联n沟道晶体管。 需要n沟道栅极晶体管来使逻辑0无劣化。 在本实施例中，p沟道栅极晶体管能够在每个时钟周期上传输输入数据。 这些传输电路通过在每个时钟周期避免不必要的通过栅极晶体管栅极电容的充电和放电来实现实质的功率节省。

公开(公告)号：EP0948841A1

公开(公告)日：1999-10-13

申请号：EP97954248.0

申请日：1997-12-18

Applicant: INTEL CORPORATION

Inventor： STAMOULIS, Georgios, I. ,  SUGISAWA, Junji ,  ZHANG, Michael, Y.

IPC: H03K17

CPC classification number: H03K17/6872

Abstract: A low power data transmission circuit includes a pass gate (20) having parallel connected n and p-channel CMOS transistors that transmit input data (DATA). To reduce power in a first embodiment, a circuit (28) disables the parallel-connected p-channel pass gate transistor except when the input data is high (logical 1). The p-channel pass gate transistor is needed to pass logical 1's without degradation. In the first embodiment, the n-channel pass gate transistor is enabled to transmit the input data on every clock cycle (CLOCK). In a second embodiment, the circuit (30) disables the parallel-connected n-channel transistor except when the input data is low (logical 0). The n-channel pass gate transistor is needed to pass logical 0's without degradation. In this embodiment, the p-channel pass gate transistor is enabled to transmit the input data on every clock cycle. These transmission circuits achieve substantial power savings by avoiding unnecessary charging and discharging of the pass gate transistors' gate capacitance on every clock cycle.

公开(公告)号：EP0948841B1

公开(公告)日：2004-05-12

申请号：EP97954248.7

申请日：1997-12-18

Applicant: INTEL CORPORATION

Inventor： STAMOULIS, Georgios, I. ,  SUGISAWA, Junji ,  ZHANG, Michael, Y.

IPC: H03K19/0948

CPC classification number: H03K17/6872

Abstract: A low power data transmission circuit includes a pass gate (20) having parallel connected n and p-channel CMOS transistors that transmit input data (DATA). To reduce power in a first embodiment, a circuit (28) disables the parallel-connected p-channel pass gate transistor except when the input data is high (logical 1). The p-channel pass gate transistor is needed to pass logical 1's without degradation. In the first embodiment, the n-channel pass gate transistor is enabled to transmit the input data on every clock cycle (CLOCK). In a second embodiment, the circuit (30) disables the parallel-connected n-channel transistor except when the input data is low (logical 0). The n-channel pass gate transistor is needed to pass logical 0's without degradation. In this embodiment, the p-channel pass gate transistor is enabled to transmit the input data on every clock cycle. These transmission circuits achieve substantial power savings by avoiding unnecessary charging and discharging of the pass gate transistors' gate capacitance on every clock cycle.