公开(公告)号：WO2017105609A1

公开(公告)日：2017-06-22

申请号：PCT/US2016/057022

申请日：2016-10-14

Applicant: INTEL CORPORATION

Inventor： MATHKAR, Akshay ,  RARAVIKAR, Nachiket Raghunath ,  TRAN, Donald Tiendung ,  JENSEN, Jerry Lee ,  FALCON, Javier A. ,  LABANOK, William Nicholas ,  SANKMAN, Robert Leon ,  STINGEL, Robert Allen

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/293 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L25/105 ,  H01L25/50 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H05K1/0298 ,  H05K1/115

Abstract: Semiconductor package interposers having high-density and high-aspect ratio encapsulated interconnects, and semiconductor package assemblies incorporating such interposers, are described. In an example, a semiconductor package interposer includes several conductive interconnects encapsulated in a polymer substrate and having height dimensions greater than a cross-sectional dimension. The semiconductor package interposer may support a first semiconductor package above a second semiconductor package and may electrically connect die pins of the first semiconductor package to die pins of the second semiconductor package.

Abstract translation: 描述了具有高密度和高纵横比封装互连的半导体封装中介层，以及包含这种中介层的半导体封装组件。 在一个示例中，半导体封装中介层包括封装在聚合物基板中并具有高于横截面尺寸的高度尺寸的多个导电互连。 半导体封装中介层可以支撑第二半导体封装上方的第一半导体封装并且可以将第一半导体封装的管脚电连接到第二半导体封装的管脚。