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    QUANTUM COMPUTING PACKAGE STRUCTURES
    3.
    发明申请
    QUANTUM COMPUTING PACKAGE STRUCTURES 审中-公开

    公开(公告)号：WO2018231212A1

    公开(公告)日：2018-12-20

    申请号：PCT/US2017/037378

    申请日：2017-06-14

    Applicant: INTEL CORPORATION

    Inventor： LIFF, Shawna ,  ELSHERBINI, Adel A. ,  SWAN, Johanna M. ,  FALCON, Javier A. ,  NAM, Ye Seul ,  CLARKE, James S. ,  ROBERTS, Jeanette M. ,  CAUDILLO, Roman

    IPC: G06N99/00 ,  B82Y10/00

    Abstract: Disclosed herein are quantum computing (QC) package structures, as well as related methods and devices. In some embodiments, a QC package may include: a package substrate; a quantum processing die coupled to the package substrate; and a lid above the quantum processing die such that the quantum processing die is between the package substrate and a top portion of the lid, wherein the lid is electrically coupled to the quantum processing die and to the package substrate. In some embodiments, a QC package may include: a package substrate; and a quantum processing die coupled to the package substrate; wherein the quantum processing die includes at least one first stop element, the package substrate includes at least one second stop element, and the first stop elements are aligned with the second stop elements to provide a mechanical stop structure between the quantum processing die and the package substrate

    SPACE-EFFICIENT UNDERFILLING TECHNIQUES FOR ELECTRONIC ASSEMBLIES
    4.
    发明申请
    SPACE-EFFICIENT UNDERFILLING TECHNIQUES FOR ELECTRONIC ASSEMBLIES 审中-公开
    电子组装的空间有效的底部填充技术

    公开(公告)号：WO2017173148A1

    公开(公告)日：2017-10-05

    申请号：PCT/US2017/025150

    申请日：2017-03-30

    Applicant: INTEL CORPORATION

    Inventor： HEPPNER, Joshua D. ,  ROUX, Serge ,  BAKER, Michael J. ,  FALCON, Javier A.

    IPC: H01L21/56 ,  H01L23/28 ,  H01L23/00 ,  H01L23/498

    Abstract: Space-efficient underfilling techniques for electronic assemblies are described. According to some such techniques, an underfilling method may comprise mounting an electronic element on a surface of a substrate, dispensing an underfill material upon the surface of the substrate within a dispense region for forming an underfill for the electronic element, and projecting curing rays upon at least a portion of the dispensed underfill material to inhibit an outward flow of dispensed underfill material from the dispense region, and the underfill material may comprise a non-visible light (NVL)-curable material. Other embodiments are described and claimed.

    Abstract translation: 描述了用于电子组件的节省空间的底部填充技术。 根据一些这样的技术，底部填充方法可以包括将电子元件安装在基板的表面上，将底部填充材料分配在分配区域内的基板的表面上以形成用于电子元件的底部填充物，并且将固化射线 分配的底部填充材料的至少一部分以抑制分配的底部填充材料从分配区向外流动，并且底部填充材料可以包括不可见光（NVL）可固化的材料。 描述并要求保护其他实施例。

    ULTRA SMALL MOLDED MODULE INTEGRATED WITH DIE BY MODULE-ON-WAFER ASSEMBLY
    5.
    发明申请
    ULTRA SMALL MOLDED MODULE INTEGRATED WITH DIE BY MODULE-ON-WAFER ASSEMBLY 审中-公开
    超小型模块与模块在晶圆组件模块集成

    公开(公告)号：WO2017111952A1

    公开(公告)日：2017-06-29

    申请号：PCT/US2015/067422

    申请日：2015-12-22

    Applicant: INTEL CORPORATION

    Inventor： YOSHIHIRO, Tomita ,  LI, Eric J. ,  LIFF, Shawna M. ,  FALCON, Javier A. ,  HEPPNER, Joshua D.

    IPC: H01L25/065 ,  H01L23/28 ,  H01L23/48

    CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L23/48 ,  H01L24/19 ,  H01L24/96 ,  H01L25/065 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2224/45099

    Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.

    Abstract translation: 本发明的实施例包括用于形成模制模块的模制模块和方法。 根据一个实施例，模制模块可以被集成到电气封装中。 根据本发明的实施例的电封装可以包括具有在至少一个表面上形成的再分布层的管芯。 模制模块可以安装到模具上。 根据一个实施例，模制模块可以包括模制层和封装在模制层内的多个部件。 来自每个组件的端子可以基本上与模制层的表面共面以便允许端子电耦合到管芯上的再分布层。 本发明的另外的实施例可以包括在模具层中形成的一个或多个模具通孔，以在部件周围提供动力输送和/或一个或多个法拉第笼。

    CARRIER FOR MICROELECTRONIC ASSEMBLIES HAVING DIRECT BONDING
    9.
    发明公开
    CARRIER FOR MICROELECTRONIC ASSEMBLIES HAVING DIRECT BONDING 审中-公开

    公开(公告)号：EP4020535A1

    公开(公告)日：2022-06-29

    申请号：EP21198763.1

    申请日：2021-09-24

    Applicant: Intel Corporation

    Inventor： LIFF, Shawna M. ,  BAKER, Michael J. ,  FALCON, Javier A.

    IPC: H01L21/67 ,  H01L21/683

    Abstract: Described herein are carrier assemblies, and related devices and methods. In some embodiments, a carrier assembly includes a carrier; a textured material including texturized microstructures coupled to the carrier; and microelectronic components mechanically coupled to the texturized microstructures. In some embodiments, a carrier assembly includes a carrier having a front side and a back side; an electrode on the front side of the carrier; a dielectric material on the electrode; a charging contact on the back side coupled to the electrode; and microelectronic components electrostatically coupled to the front side of the carrier. In some embodiments, a carrier assembly includes a carrier having a front side and a back side; electrodes on the front side; a dielectric material including texturized microstructures on the electrodes; charging contacts on the back side coupled to the plurality of electrodes; and microelectronic components mechanically and electrostatically coupled to the front side of the carrier.

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