中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

6 records (took 0.021 seconds)

    METHOD FOR SUPPORTING A VARIETY OF INSTRUCTION FETCH UNITS IN A PIPELINE WITH A SINGLE MICROPROCESSOR CORE
    2.
    发明申请
    METHOD FOR SUPPORTING A VARIETY OF INSTRUCTION FETCH UNITS IN A PIPELINE WITH A SINGLE MICROPROCESSOR CORE 审中-公开
    在单管微核心核心的管道中支持各种指导设备单元的方法

    公开(公告)号：WO1998020414A1

    公开(公告)日：1998-05-14

    申请号：PCT/US1997013504

    申请日：1997-07-30

    Applicant: INTEL CORPORATION

    Inventor： INTEL CORPORATION ,  MEYER, Paul, G. ,  STRAZDUS, Stephen ,  O'CONNOR, Dennis ,  ADELMEYER, Thomas ,  HEEB, Jay ,  TOPPS, Avery

    IPC: G06F09/30

    CPC classification number: G06F9/3802 ,  G06F9/3867

    Abstract: A processor core suitable for use with a wide variety of instruction fetch units. The processor core contains a plurality of pipe stages including an instruction pointer generation stage (52) and a decoding stage (55). The core bundles all control necessary for downstream pipeline operation with an instruction address in a first stage. The bundle is transmitted outside the core to the instruction fetch unit (59). The instruction fetch unit (59) fetches the instruction and adds it to the bundle, before forwarding the bundle as modified back within the core and down the pipeline. In this way, an external pipeline is introduced providing a connection between discontinuous pipe stages in the core. Additionally, by bundling the control signals and address information in a single bundle that traverses the external pipe stage as a group, synchronization concerns are reduced or eliminated.

    Abstract translation: 适用于各种指令提取单元的处理器核心。 处理器核心包括多个管级，包括指令指针产生级（52）和解码级（55）。 核心将下游管道运行所需的所有控制与第一阶段的指令地址进行捆绑。 捆绑包在核心外部传送到指令提取单元（59）。 指令获取单元（59）获取指令并将其添加到捆绑包中，然后在核心内向下流出管道之前转发捆绑包。 以这种方式，引入外部管道，提供核心中的不连续管段之间的连接。 此外，通过将跨越外部管道级的单个束中的控制信号和地址信息捆绑为一组，减少或消除了同步问题。

    APPARATUS AND METHOD TO PROVIDE MULTITHREADED COMPUTER PROCESSING
    3.
    发明申请
    APPARATUS AND METHOD TO PROVIDE MULTITHREADED COMPUTER PROCESSING 审中-公开
    提供多功能计算机处理的装置和方法

    公开(公告)号：WO2004102376A2

    公开(公告)日：2004-11-25

    申请号：PCT/US2004/012020

    申请日：2004-04-16

    Applicant: INTEL CORPORATION (a Delaware Corporation)

    Inventor： O'CONNOR, Dennis ,  MORROW, Michael ,  STRAZDUS, Stephen

    IPC: G06F9/00

    CPC classification number: G06F9/3891 ,  G06F9/3001 ,  G06F9/30174 ,  G06F9/3824 ,  G06F9/3851 ,  G06F9/3877 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/1027 ,  Y02D10/13

    Abstract: Briefly, in accordance with an embodiment of the invention, an apparatus and method to provide multi-threaded computer processing is provided. The apparatus may include first and second processing units adapted to share a multi-bank cache memory, an instruction pre-decode unit, a multiply-accumulate unit, a coprocessor, and/or a translation lookaside buffer (TLB). The method may include sharing use of a multi-bank cache memory between at least two transaction initiators.

    Abstract translation: 简而言之，根据本发明的实施例，提供了一种提供多线程计算机处理的装置和方法。 该装置可以包括适于共享多组高速缓冲存储器的第一和第二处理单元，指令预解码单元，乘法累加单元，协处理器和/或转换后备缓冲器（TLB）。 该方法可以包括在至少两个事务发起者之间共享多存储体高速缓冲存储器的使用。

    MULTIMEDIA COPROCESSOR CONTROL MECHANISM INCLUDING ALIGNMENT OR BROADCAST INSTRUCTIONS
    4.
    发明申请
    MULTIMEDIA COPROCESSOR CONTROL MECHANISM INCLUDING ALIGNMENT OR BROADCAST INSTRUCTIONS 审中-公开
    多媒体协同控制机制，包括对齐或广播指令

    公开(公告)号：WO2004015563A1

    公开(公告)日：2004-02-19

    申请号：PCT/US2003/024742

    申请日：2003-08-06

    Applicant: INTEL CORPORATION

    Inventor： MAGHIELSE, William ,  YU, Wing ,  PAVER, Nigel ,  JEBSON, Anthony ,  LIU, Jianwei ,  BAVARIA, Kailesh ,  PARIKH, Rupal ,  DENG, Deli ,  PATEL, Mukesh ,  FULLERTON, Mark ,  GANESHAN, Murli ,  STRAZDUS, Stephen

    IPC: G06F9/38

    CPC classification number: G06F9/30036 ,  G06F9/30032

    Abstract: A processor-based system (22) may include a main processor (24) and a coprocessor (26). The coprocessor (26) handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor (26) and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes including a byte (8 bits), a half word (16 bits), a word (32 bits), and a double word (64 bits). Two other bits indicate a saturation type.

    Abstract translation: 基于处理器的系统（22）可以包括主处理器（24）和协处理器（26）。 协处理器（26）处理包括指定要由协处理器（26）执行的数据处理操作的操作码的指令和用于识别用于协处理器指令的目标协处理器的协处理器识别字段。 两位表示四个数据大小之一，包括一个字节（8位），一个半字（16位），一个字（32位）和一个双字（64位）。 另外两个位表示饱和类型。

Patent Agency Ranking