公开(公告)号：US10037284B2

公开(公告)日：2018-07-31

申请号：US13977010

申请日：2012-10-03

Applicant: Intel Corporation

Inventor： Sai Luo ,  Xin Zhou ,  Chunxiao Lin ,  Yingzhe Shen ,  Li Shang

IPC: G06F12/10 ,  G06F13/40 ,  G06F13/32 ,  G06F12/1081

CPC classification number: G06F12/1081 ,  G06F13/32 ,  G06F13/4022 ,  G06F13/404 ,  G06F2213/0026 ,  Y02D10/14 ,  Y02D10/151

Abstract: Particular embodiments described herein can offer an electronic fabric for a processing system that includes a fabric adapter to couple to a first fabric associated with a first system and to couple to a second fabric associated with a second system. The fabric adapter is configured to pass bidirectional communications between the first system and the second system. The electronic fabric can further include an address translation agent configured to map a first physical address in a first address space of the first system to a second physical address in a second address space of the second system.

公开(公告)号：US20240232096A9

公开(公告)日：2024-07-11

申请号：US18279029

申请日：2021-03-25

Applicant: Intel Corporation

Inventor： Sanjay Kumar ,  Phillip Lantz ,  Rajesh Sankaran ,  David Hansen ,  Evgeny V. Voevodin ,  Andrew Anderson ,  Lizhen You ,  Xin Zhou ,  Nikhil Talpallikar

IPC: G06F12/1009

CPC classification number: G06F12/1009

Abstract: An embodiment of an integrated circuit may comprise an array of hardware counters, and circuitry communicatively coupled to the array of hardware counters, the circuitry to count accesses to one or more selected pages of a memory with the array of hardware counters. Other embodiments are disclosed and claimed.

公开(公告)号：US20240134803A1

公开(公告)日：2024-04-25

申请号：US18279029

申请日：2021-03-24

Applicant: Intel Corporation

Inventor： Sanjay Kumar ,  Phillip Lantz ,  Rajesh Sankaran ,  David Hansen ,  Evgeny V. Voevodin ,  Andrew Anderson ,  Lizhen You ,  Xin Zhou ,  Nikhil Talpallikar

IPC: G06F12/1009

CPC classification number: G06F12/1009

Abstract: An embodiment of an integrated circuit may comprise an array of hardware counters, and circuitry communicatively coupled to the array of hardware counters, the circuitry to count accesses to one or more selected pages of a memory with the array of hardware counters. Other embodiments are disclosed and claimed.