公开(公告)号：US20220399324A1

公开(公告)日：2022-12-15

申请号：US17344348

申请日：2021-06-10

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Adel A. Elsherbini ,  Kimin Jun ,  Johanna M. Swan ,  Shawna M. Liff ,  Sathya Narasimman Tiagaraj ,  Gerald S. Pasdast ,  Aleksandar Aleksov ,  Feras Eid

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/00

Abstract: A die assembly comprising: a first component layer having conductive through-connections in an insulator, a second component layer comprising a die, and an active device layer (ADL) at an interface between the first component layer and the second component layer. The ADL comprises active elements electrically coupled to the first component layer and the second component layer. The die assembly further comprises a bonding layer electrically coupling the ADL to the second component layer. In some embodiments, the die assembly further comprises another ADL at another interface between the first component layer and a package support opposite to the interface. The first component layer may comprise another die having through-substrate vias (TSVs). The die and the another die may be fabricated using different process nodes.

公开(公告)号：US20220399277A1

公开(公告)日：2022-12-15

申请号：US17345969

申请日：2021-06-11

Applicant: INTEL CORPORATION

Inventor： Adel A. Elsherbini ,  Scott E. Siers ,  Sathya Narasimman Tiagaraj ,  Gerald S. Pasdast ,  Zhiguo Qian ,  Kalyan C. Kolluru ,  Vivek Kumar Rajan ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

Abstract: An Integrated Circuit (IC), comprising a first conductive trace on a first die, a second conductive trace on a second die, and a conductive pathway electrically coupling the first conductive trace with the second conductive trace. The second die is coupled to the first die with interconnects. The conductive pathway comprises a portion of the interconnects located proximate to a periphery of a region in the first die through which the first conductive trace is not routable. In some embodiments, the conductive pathway reroutes electrical connections away from the region. The region comprises a high congestion zone having high routing density in some embodiments. In other embodiments, the region comprises a “keep-out” zone.

公开(公告)号：US20230230923A1

公开(公告)日：2023-07-20

申请号：US17824974

申请日：2022-05-26

Applicant: Intel Corporation

Inventor： Gerald Pasdast ,  Zhiguo Qian ,  Sathya Narasimman Tiagaraj ,  Lakshmipriya Seshan ,  Peipei Wang ,  Debendra Das Sharma ,  Srikanth Nimmagadda ,  Zuoguo Wu ,  Swadesh Choudhary ,  Narasimha Lanka

IPC: H01L23/538 ,  H01L25/16 ,  H01L23/00

CPC classification number: H01L23/5382 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/16 ,  H01L2224/16225

Abstract: A microelectronic device, a semiconductor package including the device, an IC device assembly including the package, and a method of making the device. The device includes a substrate; physical layer (PHY) circuitry on the substrate including a plurality of receive (RX) circuits and a plurality of transmit (TX) circuits; electrical contact structures at a bottom surface of the device; signal routing paths extending between the electrical contact structures on one hand, and, on another hand, at least some of the RX circuits or at least some of the TX circuits; and electrical pathways leading to the PHY circuitry and configured such that at least one of: an enable signal input to the device is to travel through at least some of the electrical pathways to enable a portion of the PHY circuitry; or a disable signal input to the device is to travel through at least some of the electrical pathways to disable a corresponding portion of the PHY circuitry.

公开(公告)号：US20220197321A1

公开(公告)日：2022-06-23

申请号：US17128073

申请日：2020-12-19

Applicant: Intel Corporation

Inventor： Sathya Narasimman Tiagaraj ,  Gerald Pasdast ,  Edward Burton

IPC: G05F1/575 ,  G06F1/26

Abstract: A dual-loop low-drop (LDO) regulator having a first loop which is an analog loop that compares the voltage on the output supply node with a reference, and generates a bias or voltage control to control a strength of a final power switch. The first loop regulates the output voltage relative to a reference voltage by minimizing the error between the two voltages. A second loop (digital loop) that controls a current source which injects current on the gate of the final power switch to boost current for a load. The second loop is an auxiliary loop that boosts the current load for a set interval until the tracking bandwidth of the LDO resolves the error in the output, thereby reducing the peak-to-peak noise. The quiescent current is not increased a lot by the second loop since the second loop circuit is on for a fraction of the entire LDO operation.

公开(公告)号：US20210202377A1

公开(公告)日：2021-07-01

申请号：US16727747

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Mauro Kobrinsky ,  Shawna Liff ,  Johanna Swan ,  Gerald Pasdast ,  Sathya Narasimman Tiagaraj

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: An integrated circuit device may be formed including an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes a first level comprising a first dielectric material layer, a second level on the first level, wherein the second level comprises a second dielectric material layer, a third level on the second level, wherein the third level comprises a third dielectric material layer, at least one power/ground structure in the second level, and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.

公开(公告)号：US12288746B2

公开(公告)日：2025-04-29

申请号：US16727747

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Mauro Kobrinsky ,  Shawna Liff ,  Johanna Swan ,  Gerald Pasdast ,  Sathya Narasimman Tiagaraj

IPC: H01L23/52 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: An integrated circuit device may be formed including an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes a first level comprising a first dielectric material layer, a second level on the first level, wherein the second level comprises a second dielectric material layer, a third level on the second level, wherein the third level comprises a third dielectric material layer, at least one power/ground structure in the second level, and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.

公开(公告)号：US12164319B2

公开(公告)日：2024-12-10

申请号：US17128073

申请日：2020-12-19

Applicant: Intel Corporation

Inventor： Sathya Narasimman Tiagaraj ,  Gerald Pasdast ,  Edward Burton

IPC: G05F1/575 ,  G06F1/26

Abstract: A dual-loop low-drop (LDO) regulator having a first loop which is an analog loop that compares the voltage on the output supply node with a reference, and generates a bias or voltage control to control a strength of a final power switch. The first loop regulates the output voltage relative to a reference voltage by minimizing the error between the two voltages. A second loop (digital loop) that controls a current source which injects current on the gate of the final power switch to boost current for a load. The second loop is an auxiliary loop that boosts the current load for a set interval until the tracking bandwidth of the LDO resolves the error in the output, thereby reducing the peak-to-peak noise. The quiescent current is not increased a lot by the second loop since the second loop circuit is on for a fraction of the entire LDO operation.

公开(公告)号：US20240063132A1

公开(公告)日：2024-02-22

申请号：US17820993

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Scott E. Siers ,  Gerald S. Pasdast ,  Johanna M. Swan ,  Henning Braunisch ,  Kimin Jun ,  Jiraporn Seangatith ,  Shawna M. Liff ,  Mohammad Enamul Kabir ,  Sathya Narasimman Tiagaraj

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L24/08 ,  H01L24/16 ,  H01L24/80 ,  H01L24/05 ,  H01L25/0652 ,  H01L25/0657 ,  H01L23/5383 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/16225 ,  H01L2224/08145 ,  H01L2224/08121 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/37001 ,  H01L2924/3841 ,  H01L2924/3512

Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of IC dies, adjacent layers in the plurality of layers being coupled together by first interconnects and a package substrate coupled to the plurality of layers by second interconnects. A first layer in the plurality of layers comprises a dielectric material surrounding a first IC die in the first layer, a second layer in the plurality of layers is adjacent and non-coplanar with the first layer, the second layer comprises a first circuit region and a second circuit region separated by a third circuit region, the first circuit region and the second circuit region are bounded by respective guard rings, and the first IC die comprises conductive pathways conductively coupling conductive traces in the first circuit region with conductive traces in the second circuit region.

公开(公告)号：US20240030172A1

公开(公告)日：2024-01-25

申请号：US18479014

申请日：2023-09-30

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Peter Z. Onufryk ,  Gerald S. Pasdast ,  Sathya Narasimman Tiagaraj

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/16 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2224/16145 ,  H01L2924/1431 ,  H01L2924/381

Abstract: Methods and apparatus relating to a Universal Chiplet Interconnect Express™ (UCIe™)-Three Dimensional (UCIe-3D™) interconnect which may be utilized as an on-package interconnect are described. In one embodiment, an interconnect communicatively couples a first physical layer module of a first chiplet on a semiconductor package to a second physical layer module of a second chiplet on the semiconductor package. A first Network-on-chip Controller (NoC) logic circuitry controls the first physical layer module. A second NoC logic circuitry controls the second physical layer module. Other embodiments are also claimed and disclosed.

公开(公告)号：US20230163098A1

公开(公告)日：2023-05-25

申请号：US17531374

申请日：2021-11-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  William J. Lambert ,  Krishna Bharath ,  Shawna M. Liff ,  Nicolas Butzen ,  Georgios Dogiamis ,  Gerald S. Pasdast ,  Vivek Kumar Rajan ,  Sathya Narasimman Tiagaraj ,  Timothy Francis Schmidt

IPC: H01L25/065

CPC classification number: H01L25/0652 ,  H01L25/18

Abstract: Embodiments of the present disclosure provide a microelectronic assembly comprising: an integrated circuit (IC) die in a first layer and a plurality of IC dies in a second layer, at least two adjacent IC dies in the plurality being electrically coupled along their proximate edges by the IC die. The first layer and the second layer are electrically and mechanically coupled by interconnects having a pitch of less than 10 micrometers between adjacent interconnects, and the IC die comprises capacitors and voltage regulator circuitry.