公开(公告)号：US11508577B2

公开(公告)日：2022-11-22

申请号：US16024694

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Matthew Metz ,  Willy Rachmady ,  Sean Ma ,  Nicholas Minutillo ,  Cheng-Ying Huang ,  Tahir Ghani ,  Jack Kavalieros ,  Anand Murthy ,  Harold Kennel

IPC: H01L21/02 ,  H01L29/20 ,  H01L29/04 ,  H01L29/78 ,  H01L27/12

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device including a substrate and an insulator layer above the substrate. A channel area may include an III-V material relaxed grown on the insulator layer. A source area may be above the insulator layer, in contact with the insulator layer, and adjacent to a first end of the channel area. A drain area may be above the insulator layer, in contact with the insulator layer, and adjacent to a second end of the channel area that is opposite to the first end of the channel area. The source area or the drain area may include one or more seed components including a seed material with free surface. Other embodiments may be described and/or claimed.

公开(公告)号：US20200235013A1

公开(公告)日：2020-07-23

申请号：US16635108

申请日：2017-08-24

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Sean Ma ,  Justin R. Weber ,  Rishabh Mehandru ,  Stephen M. Cea ,  Patrick Morrow ,  Patrick H. Keys

IPC: H01L21/822 ,  H01L29/417 ,  H01L21/8258 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311

Abstract: Stacked finFET structures including a fin having at least a first layer of semiconductor material stacked over or under a second layer of semiconductor material. The first and second layers may include a Group IV semiconductor material layer and a Group III-V semiconductor material layer, for example. A stacked finFET may include an N-type finFET stacked over or under a P-type finFET, the two finFETs may have channel portions within the different semiconductor material layers. Channel portions of the first and second layers of semiconductor material may be coupled to separate gate electrodes that are vertically aligned. Channel portions of the first and second layers of semiconductor material may be vertically separated by subfin portions of the first and second layers. Different layers of dielectric material adjacent to the subfin portions may improve electrical isolation between the channel portions, for example as a source of fixed charge or impurity dopants.

公开(公告)号：US20190333990A1

公开(公告)日：2019-10-31

申请号：US16475031

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Patrick Keys ,  Sean Ma ,  Stephen Cea ,  Rishabh Mehandru

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L21/78 ,  H01L29/08 ,  H01L21/56 ,  H01L21/306 ,  H01L21/3105 ,  H01L29/40 ,  H01L29/66 ,  H01L23/31 ,  H01L27/088

Abstract: An apparatus is provided which comprises: a plurality of nanowire transistors stacked vertically, wherein each nanowire transistor of the plurality of nanowire transistors comprises a corresponding nanowire of a plurality of nanowires; and a gate stack, wherein the gate stack fully encircles at least a section of each nanowire of the plurality of nanowires.

公开(公告)号：US11527613B2

公开(公告)日：2022-12-13

申请号：US17145114

申请日：2021-01-08

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Patrick Keys ,  Sean Ma ,  Stephen Cea ,  Rishabh Mehandru

IPC: H01L29/06 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: An apparatus is provided which comprises: a plurality of nanowire transistors stacked vertically, wherein each nanowire transistor of the plurality of nanowire transistors comprises a corresponding nanowire of a plurality of nanowires; and a gate stack, wherein the gate stack fully encircles at least a section of each nanowire of the plurality of nanowires.

公开(公告)号：US11245038B2

公开(公告)日：2022-02-08

申请号：US16490503

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Yih Wang ,  Abhishek Sharma ,  Sean Ma ,  Van H. Lee

IPC: H01L29/786 ,  H01L27/108 ,  H01L29/66

Abstract: Vertical thin film transistors (TFTs) including a gate electrode pillar clad with a gate dielectric. The gate dielectric is further clad with a semiconductor layer. Source or drain metallization is embedded in trenches formed in an isolation dielectric adjacent to separate regions of the semiconductor layer. During TFT operation, biasing of the gate electrode can induce one or more transistor channel within the semiconductor layer, electrically coupling together the source and drain metallization. A width of the channel may be proportional to a height of the gate electrode pillar clad by the semiconductor layer, while a length of the channel may be proportional to the spacing between contacts occupied by the semiconductor layer. In some embodiments, a memory device may include cells comprising a vertical thin film select transistor and a capacitor (1TFT-1C).

公开(公告)号：US20210159312A1

公开(公告)日：2021-05-27

申请号：US17145114

申请日：2021-01-08

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Patrick Keys ,  Sean Ma ,  Stephen Cea ,  Rishabh Mehandru

IPC: H01L29/06 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: An apparatus is provided which comprises: a plurality of nanowire transistors stacked vertically, wherein each nanowire transistor of the plurality of nanowire transistors comprises a corresponding nanowire of a plurality of nanowires; and a gate stack, wherein the gate stack fully encircles at least a section of each nanowire of the plurality of nanowires.

公开(公告)号：US12142689B2

公开(公告)日：2024-11-12

申请号：US17940949

申请日：2022-09-08

Applicant: Intel Corporation

Inventor： Sean Ma ,  Abhishek Sharma ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Van H. Le

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/417 ,  H01L29/49 ,  H01L29/78

Abstract: A transistor is described. The transistor includes a substrate, a first semiconductor structure above the substrate, a second semiconductor structure above the substrate, a source contact that includes a first metal structure that contacts a plurality of surfaces of the first semiconductor structure and a drain contact that includes a second metal structure that contacts a plurality of surfaces of the second semiconductor structure. The transistor also includes a gate below a back side of the substrate.

公开(公告)号：US11881517B2

公开(公告)日：2024-01-23

申请号：US17724331

申请日：2022-04-19

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Cory Weber ,  Van H. Le ,  Sean Ma

IPC: H01L29/47 ,  H01L29/66 ,  H01L29/45 ,  H01L29/786 ,  H01L29/423 ,  H10B12/00 ,  H10B63/00

CPC classification number: H01L29/47 ,  H01L29/42356 ,  H01L29/66742 ,  H01L29/786 ,  H10B12/30 ,  H10B63/30

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a gate electrode above the substrate, and a channel layer above the substrate, separated from the gate electrode by a gate dielectric layer. The transistor further includes a contact electrode above the channel layer and in contact with a contact area of the channel layer. The contact area has a thickness determined based on a Schottky barrier height of a Schottky barrier formed at an interface between the contact electrode and the contact area, a doping concentration of the contact area, and a contact resistance at the interface between the contact electrode and the contact area. Other embodiments may be described and/or claimed.

公开(公告)号：US11862729B2

公开(公告)日：2024-01-02

申请号：US17584260

申请日：2022-01-25

Applicant: Intel Corporation

Inventor： Yih Wang ,  Abhishek Sharma ,  Sean Ma ,  Van H. Le

IPC: H01L29/786 ,  H01L29/66 ,  H10B12/00

CPC classification number: H01L29/78642 ,  H01L29/66742 ,  H10B12/053 ,  H10B12/34 ,  H10B12/488

Abstract: Vertical thin film transistors (TFTs) including a gate electrode pillar clad with a gate dielectric. The gate dielectric is further clad with a semiconductor layer. Source or drain metallization is embedded in trenches formed in an isolation dielectric adjacent to separate regions of the semiconductor layer. During TFT operation, biasing of the gate electrode can induce one or more transistor channel within the semiconductor layer, electrically coupling together the source and drain metallization. A width of the channel may be proportional to a height of the gate electrode pillar clad by the semiconductor layer, while a length of the channel may be proportional to the spacing between contacts occupied by the semiconductor layer. In some embodiments, a memory device may include cells comprising a vertical thin film select transistor and a capacitor (1TFT-1C).

公开(公告)号：US11756998B2

公开(公告)日：2023-09-12

申请号：US17576765

申请日：2022-01-14

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Tahir Ghani ,  Jack Kavalieros ,  Anand Murthy ,  Harold Kennel ,  Gilbert Dewey ,  Matthew Metz ,  Willy Rachmady ,  Sean Ma ,  Nicholas Minutillo

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/205 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/0684 ,  H01L21/02543 ,  H01L21/02546 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/7851

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.