公开(公告)号：WO2018063396A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/055012

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： LILAK, Aaron D. ,  THEOFANIS, Patrick ,  MORROW, Patrick ,  MEHANDRU, Rishabh ,  CEA, Stephen M.

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L27/11575

Abstract: An apparatus including an array of at least two vertically stacked layers of integrated circuit device components separated by a dielectric layer on a substrate, wherein each of the at least two vertically stacked layers includes a laterally disposed contact point; and an electrically conductive interconnection coupled to a lateral edge of the contact point of each of the at least two vertically stacked layers and bridging the dielectric layer. A method including forming an array of at least two vertically stacked layers of integrated circuit device components separated by a dielectric layer on a substrate, forming a trench that exposes a lateral contact point of each of the at least two vertically stacked layers; depositing a polymer in the trench, wherein the polymer preferentially aligns to a material of the lateral contact point and bridges the dielectric layer; and modifying or replacing the polymer with an electrically conductive material.

Abstract translation: 一种装置，包括由衬底上的电介质层分开的至少两个垂直堆叠的集成电路器件部件的阵列，其中所述至少两个垂直堆叠的层中的每一个包括横向布置的接触点 ; 以及导电互连，所述导电互连耦合到所述至少两个垂直堆叠层中的每一个的所述接触点的横向边缘并桥接所述介电层。 一种方法，包括：在衬底上形成由电介质层分开的至少两个垂直堆叠的集成电路器件部件层的阵列;形成暴露所述至少两个垂直堆叠层中的每一个的侧向接触点的沟槽; 在所述沟槽中沉积聚合物，其中所述聚合物优先对准所述横向接触点的材料并桥接所述电介质层; 并用导电材料改性或替换聚合物。

公开(公告)号：WO2018169528A1

公开(公告)日：2018-09-20

申请号：PCT/US2017/022585

申请日：2017-03-15

Applicant: INTEL CORPORATION

Inventor： LILAK, Aaron D. ,  THEOFANIS, Patrick ,  WEBER, Cory E. ,  CEA, Stephen M. ,  MEHANDRU, Rishabh

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: An integrated circuit structure is provided which comprises: a stack of source regions of a stack of transistors and a stack of drain regions of the stack of transistors; and a gate stack that forms gate regions for the stack of transistors, wherein the gate stack comprises traces of a first polymer of a block copolymer, the block copolymer comprising the first polymer and a second polymer.

公开(公告)号：WO2015199721A1

公开(公告)日：2015-12-30

申请号：PCT/US2014/044594

申请日：2014-06-27

Applicant: INTEL CORPORATION

Inventor： MUNOZ, Jorge A. ,  NIKONOV, Dmitri E. ,  KUHN, Kelin J. ,  THEOFANIS, Patrick ,  PAWASHE, Chytra ,  LIN, Kevin ,  KIM, Seiyon

IPC: B81B7/02

CPC classification number: B82B1/005 ,  B81B3/0016 ,  B81B7/02 ,  B81B2201/014 ,  B81B2203/0118 ,  B82B1/002 ,  B82B3/0023 ,  B82Y15/00 ,  B82Y25/00 ,  B82Y40/00 ,  H01H1/0094 ,  H01H1/54 ,  H01H59/0009 ,  H01L29/66227 ,  H01L29/82 ,  H01L29/84 ,  Y10S977/732 ,  Y10S977/838 ,  Y10S977/888 ,  Y10S977/938

Abstract: Nanoelectromechanical (NEMS) devices having nanomagnets for an improved range of operating voltages and improved control of dimensions of a cantilever are described. For example, in an embodiment, a nanoelectromechanical (NEMS) device includes a substrate layer, a first magnetic layer disposed above the substrate layer, a first dielectric layer disposed above the first magnetic layer, a second dielectric disposed above the first dielectric layer, and a cantilever disposed above the second dielectric layer. The cantilever bends from a first position to a second position towards the substrate layer when a voltage is applied to the cantilever.

Abstract translation: 描述了具有改进的工作电压范围的纳米磁体和改进的悬臂尺寸控制的纳米机电（NEMS）装置。 例如，在一个实施例中，纳米机电（NEMS）器件包括衬底层，设置在衬底层上方的第一磁性层，设置在第一磁性层上方的第一介电层，设置在第一介电层上方的第二电介质，以及 布置在第二介电层上方的悬臂。 当向悬臂施加电压时，悬臂从第一位置弯曲到第二位置朝向衬底层。

公开(公告)号：WO2019066829A1

公开(公告)日：2019-04-04

申请号：PCT/US2017/053852

申请日：2017-09-28

Applicant: INTEL CORPORATION ,  LILAK, Aaron D. ,  THEOFANIS, Patrick ,  KENCKE, David L. ,  KOTLYAR, Roza

Inventor： LILAK, Aaron D. ,  THEOFANIS, Patrick ,  KENCKE, David L. ,  KOTLYAR, Roza

IPC: H01L45/00

CPC classification number: H01L27/249 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

Abstract: An integrated circuit structure includes a stack of alternating first conductive layers and insulator layers. A plurality of etch pits are through the first conductive layers. A plurality of selectors are in the etch pits adjacent to the first conductive layers. A memory material layer is adjacent to the plurality of selectors in the etch pits, wherein one of the plurality of selectors and the memory material layer is self-aligned and has a hemispherical side facing the corresponding etch pit.

公开(公告)号：WO2019005161A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040501

申请日：2017-06-30

Applicant: INTEL CORPORATION ,  KRYSAK, Marie ,  BLACKWELL, James M. ,  THEOFANIS, Patrick ,  BRISTOL, Robert L.

Inventor： KRYSAK, Marie ,  BLACKWELL, James M. ,  THEOFANIS, Patrick ,  BRISTOL, Robert L.

IPC: H01L21/033 ,  H01L21/02

CPC classification number: H01L21/0334 ,  G03F7/0042 ,  G03F7/38 ,  G03F7/405 ,  H01L21/0274 ,  H01L21/0332

Abstract: Techniques and mechanisms for patterning a resist using a quencher to limit an irradiation-induced reaction. In an embodiment, the resist material includes nanoclusters and ligands which promote solubility of the nanoclusters. An inorganic molecule of the nanoclusters includes one of a transition metal element, a lanthanide element, an actinide element, or a main group element. Irradiation of the resist material initiates chemical reaction with the ligands, wherein the reaction results in larger structures begin formed with the inorganic nanoparticles. A compound disposed in or adjacent to the resist material provides a quencher which reacts with a by-product of the irradiation-induced reaction. The quencher prevents the by-product from continuing the irradiation-induced reaction in the resist material. In another embodiment, the by-product is one of an electron and a radical.

公开(公告)号：WO2018125065A1

公开(公告)日：2018-07-05

申请号：PCT/US2016/068764

申请日：2016-12-27

Applicant: INTEL CORPORATION

Inventor： PAWASHE, Chytra ,  THEOFANIS, Patrick ,  CAUDILLO, Roman ,  TORRES, Jessica, M.

IPC: H01L29/06 ,  H01L21/8238 ,  H01L21/02 ,  H01L27/115 ,  H01L29/16 ,  H01L27/06

CPC classification number: B82Y15/00 ,  B82Y10/00 ,  H01H1/0094 ,  H01H59/0009 ,  H01L29/0673 ,  H01L29/1606 ,  H01L29/786

Abstract: An apparatus is provided which comprises: a beam disposed in a void disposed above a substrate, the beam having anchored portions at opposite ends, wherein the beam comprises an atomic thick layer of 2-D material, a first conductive region cantilevered into the void from a surface of the substrate and spaced apart from the beam, and first and second gate electrodes disposed adjacent the surface of the substrate and spaced apart on opposite sides of the first conductive region. Other embodiments are also disclosed and claimed.

公开(公告)号：EP3160897A1

公开(公告)日：2017-05-03

申请号：EP14896176.6

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： MUNOZ, Jorge A. ,  NIKONOV, Dmitri E. ,  KUHN, Kelin J. ,  THEOFANIS, Patrick ,  PAWASHE, Chytra ,  LIN, Kevin ,  KIM, Seiyon

IPC: B81B7/02

CPC classification number: B82B1/005 ,  B81B3/0016 ,  B81B7/02 ,  B81B2201/014 ,  B81B2203/0118 ,  B82B1/002 ,  B82B3/0023 ,  B82Y15/00 ,  B82Y25/00 ,  B82Y40/00 ,  H01H1/0094 ,  H01H1/54 ,  H01H59/0009 ,  H01L29/66227 ,  H01L29/82 ,  H01L29/84 ,  Y10S977/732 ,  Y10S977/838 ,  Y10S977/888 ,  Y10S977/938

Abstract: Nanoelectromechanical (NEMS) devices having nanomagnets for an improved range of operating voltages and improved control of dimensions of a cantilever are described. For example, in an embodiment, a nanoelectromechanical (NEMS) device includes a substrate layer, a first magnetic layer disposed above the substrate layer, a first dielectric layer disposed above the first magnetic layer, a second dielectric disposed above the first dielectric layer, and a cantilever disposed above the second dielectric layer. The cantilever bends from a first position to a second position towards the substrate layer when a voltage is applied to the cantilever.

Abstract translation: 描述了具有用于改进的操作电压范围的纳米磁体的纳机电（NEMS）装置和改进的悬臂尺寸控制。 例如，在一个实施例中，纳米机电（NEMS）器件包括衬底层，设置在衬底层上方的第一磁性层，设置在第一磁性层上方的第一电介质层，设置在第一电介质层上方的第二电介质，以及 设置在第二介电层上方的悬臂。 当向悬臂施加电压时，悬臂从第一位置弯曲到第二位置朝向衬底层。