公开(公告)号：WO2023048886A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/041429

申请日：2022-08-24

Applicant: INTEL CORPORATION

Inventor： SHANBHOGUE, Vedvyas ,  SAHITA, Ravi ,  KAKAIYA, Utkarsh ,  BASAK, Abhishek ,  ALBION, Lee ,  SCHMOLE, Filip ,  VAKHARWALA, Rupin ,  ABRAHAM, Vinit ,  MAKARAM, Raghunandan

IPC: G06F9/455 ,  G06F21/53

Abstract: Apparatus and method for role-based register protection. For example, one embodiment of an apparatus comprises: one or more processor cores to execute instructions and process data, the one or more processor cores to execute one or more security instructions to protect a virtual machine or trusted application from a virtual machine monitor (VMM) or operating system (OS); an interconnect fabric to couple the one or more processor cores to a device; and security hardware logic to determine whether to allow a read or write transaction directed to a protected register to proceed over the interconnect fabric, the security hardware logic to evaluate one or more security attributes associated with an initiator of the transaction to make the determination.

公开(公告)号：EP4449249A1

公开(公告)日：2024-10-23

申请号：EP22908179.9

申请日：2022-10-19

Applicant: Intel Corporation

Inventor： GAYEN, Saurabh ,  LANTZ, Philip ,  RANGANATHAN, Narayan ,  JOSHI, Dhananjay ,  SANKARAN, Rajesh ,  KAKAIYA, Utkarsh

IPC: G06F9/455 ,  G06F9/50 ,  G06F9/48

公开(公告)号：EP4405814A1

公开(公告)日：2024-07-31

申请号：EP22873394.5

申请日：2022-08-24

Applicant: Intel Corporation

Inventor： SHANBHOGUE, Vedvyas ,  SAHITA, Ravi ,  KAKAIYA, Utkarsh ,  BASAK, Abhishek ,  ALBION, Lee ,  SCHMOLE, Filip ,  VAKHARWALA, Rupin ,  MATHEW ABRAHAM, Vinit ,  MAKARAM, Raghunandan

IPC: G06F9/455 ,  G06F21/53

CPC classification number: G06F13/4027 ,  G06F21/71 ,  G06F21/79 ,  G06F9/45558 ,  G06F2009/4558720130101 ,  G06F2009/4557920130101

公开(公告)号：EP4254203A1

公开(公告)日：2023-10-04

申请号：EP23155456.9

申请日：2023-02-07

Applicant: INTEL Corporation

Inventor： KRISHNAN, Vidhya ,  CHHABRA, Siddhartha ,  PUFFER, David ,  SHAH, Ankur ,  NEMIROFF, Daniel ,  KAKAIYA, Utkarsh

IPC: G06F12/109 ,  G06F12/14 ,  G06F11/10 ,  G06F21/53 ,  G06F21/78

Abstract: Device memory protection for supporting trust domains is described. An example of a computer-readable storage medium includes instructions for allocating device memory for one or more trust domains (TDs) in a system including one or more processors and a graphics processing unit (GPU); allocating a trusted key ID for a TD of the one or more TDs; creating LMTT (Local Memory Translation Table) mapping for address translation tables, the address translation tables being stored in a device memory of the GPU; transitioning the TD to a secure state; and receiving and processing a memory access request associated with the TD, processing the memory access request including accessing a secure version of the address translation tables.

公开(公告)号：EP4020221A1

公开(公告)日：2022-06-29

申请号：EP21198566.8

申请日：2021-09-23

Applicant: INTEL Corporation

Inventor： SHANBHOGUE, Vedvyas ,  GAUR, Jayesh ,  FEGHALI, Wajdi K. ,  GOPAL, Vinodh ,  KAKAIYA, Utkarsh

IPC: G06F12/08 ,  G06F12/0886 ,  G06F12/1009

Abstract: An embodiment of an integrated circuit may comprise, coupled to a core, a hardware decompression accelerator, a compressed cache, a processor and communicatively coupled to the hardware decompression accelerator and the compressed cache, and memory and communicatively coupled to the processor, wherein the memory stores microcode instructions which when executed by the processor causes the processor to store a first address to a decompression work descriptor, retrieve a second address where a compressed page is stored in the compressed cache from the decompression work descriptor at the first address in response to an indication of a page fault, and send instructions to the hardware decompression accelerator to decompress the compressed page at the second address. Other embodiments are disclosed and claimed.