公开(公告)号：EP1444798A4

公开(公告)日：2007-12-12

申请号：EP02786716

申请日：2002-11-13

Applicant: INTERDIGITAL TECH CORP

Inventor： BECKER PETER E ,  SUPPLEE STEPHAN SHANE

IPC: G06F17/16 ,  G06F17/12 ,  H04B1/707 ,  H04B7/155 ,  H04B15/00 ,  H04K1/00 ,  H04L27/30

CPC classification number: G06F17/16 ,  G06F17/12 ,  H04B1/7105 ,  H04B1/71055

Abstract: Processing elements (54-54N) are utilized for solving linear systems. One embodiment (Fig. 3B) projects matrix elements along a diagonal of the matrix onto scalar processing elements to determine a Cholesky factor. Another embodiment uses a two-dimensional scalar array to determine a Cholesky factor. For matrices having a limited bandwidth, the processors (54-54N) may be used to reduce the number of processors used.

公开(公告)号：EP1509837A4

公开(公告)日：2005-07-06

申请号：EP03731379

申请日：2003-05-27

Applicant: INTERDIGITAL TECH CORP

Inventor： BECKER PETER E

IPC: G06F7/52 ,  G06F7/48 ,  G06F7/523 ,  G06F7/535 ,  G06F17/16

CPC classification number: G06F7/4806 ,  G06F7/535

Abstract: A circuit performs complex division and dual complex multiplication. The circuit has a plurality of multipliers (20, 22, 24, 26, 38, 44, 56, 58). Each of the plurality of multipliers is used in both the complex division and the dual complex multiplications. The circuit also has a plurality of components (30, 32) capable of adding and subtracting. Each adding and subtracting component is used during the complex division and the dual complex multiplication and switches between operation as an adder and a subtractor between performing the complex division and the dual complex multiplication. Preferred potential uses for the circuit are in a receiver of a user equipment or a base station. The circuit is used in a fast Fourier transform (FFT) based channel estimation or a FFT based data detection.

公开(公告)号：CA2466684A1

公开(公告)日：2003-05-22

申请号：CA2466684

申请日：2002-11-13

Applicant: INTERDIGITAL TECH CORP

Inventor： SUPPLEE STEPHAN SHANE ,  BECKER PETER E

IPC: G06F17/16 ,  G06F17/12 ,  H04B1/707 ,  H04B7/155 ,  H04B15/00 ,  H04K1/00 ,  H04L27/30

Abstract: Processing elements (54-54N) are utilized for solving linear systems. One embodiment (Fig. 3B) projects matrix elements along a diagonal of the matrix onto scalar processing elements to determine a Cholesky factor. Another embodiment uses a two-dimensional scalar array to determine a Cholesky facto r. For matrices having a limited bandwidth, the processors (54-54N) may be used to reduce the number of processors used.

公开(公告)号：AU2003241628A1

公开(公告)日：2003-12-12

申请号：AU2003241628

申请日：2003-05-27

Applicant: INTERDIGITAL TECH CORP

Inventor： BECKER PETER E

IPC: G06F7/52 ,  G06F7/48 ,  G06F7/523 ,  G06F7/535 ,  G06F17/16

Abstract: A circuit is capable of performing a complex division and dual complex multiplication. The complex division involves dividing a first complex value by a second complex value and the dual complex multiplication involves multiplying a third complex value by a fourth complex value and a fifth complex value by a sixth complex value. The circuit comprises a first input configured to receive the first and second complex values when the circuit is performing the complex division and the third and fourth complex values when the circuit is performing the dual complex multiplication. A second input is configured to receive the second complex value when performing the complex division and the fifth and sixth complex values when performing dual complex multiplication. A first output produces a result of complex multiplication of the third and fourth complex values when the circuit is performing the dual complex multiplication. A second output produces a result of the complex division of the first complex value divided by the second complex value when the circuit is performing the complex division and complex multiplication of the fifth complex value by the sixth complex value when performing the dual complex multiplication.

公开(公告)号：CA2486811A1

公开(公告)日：2003-12-04

申请号：CA2486811

申请日：2003-05-27

Applicant: INTERDIGITAL TECH CORP

Inventor： BECKER PETER E

IPC: G06F7/52 ,  G06F7/48 ,  G06F7/523 ,  G06F7/535 ,  G06F17/16

Abstract: A circuit performs complex division and dual complex multiplication. The circuit has a plurality of multipliers (20, 22, 24, 26, 38, 44, 56, 58). Eac h of the plurality of multipliers is used in both the complex division and the dual complex multiplications. The circuit also has a plurality of components (30, 32) capable of adding and subtracting. Each adding and subtracting component is used during the complex division and the dual complex multiplication and switches between operation as an adder and a subtractor between performing the complex division and the dual complex multiplication. Preferred potential uses for the circuit are in a receiver of a user equipme nt or a base station. The circuit is used in a fast Fourier transform (FFT) bas ed channel estimation or a FFT based data detection.