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    PHYSICAL LAYER PROCESSING FOR A WIRELESS COMMUNICATION SYSTEM USING CODE DIVISION MULTIPLE ACCESS
    2.
    发明申请
    PHYSICAL LAYER PROCESSING FOR A WIRELESS COMMUNICATION SYSTEM USING CODE DIVISION MULTIPLE ACCESS 审中-公开
    使用代码段多路访问的无线通信系统的物理层处理

    公开(公告)号：WO02084889A3

    公开(公告)日：2003-04-17

    申请号：PCT/US0211811

    申请日：2002-04-16

    Applicant: INTERDIGITAL TECH CORP

    Inventor： CASTOR DOUGLAS R ,  MCCLELLAN GEORGE W ,  MORABITO JOSEPH T

    IPC: H03M13/23 ,  H03M13/27 ,  H03M13/29 ,  H04B1/69 ,  H04B7/155 ,  H04B7/208 ,  H04B7/212 ,  H04B7/216 ,  H04B7/26 ,  H04J3/00 ,  H04J3/02 ,  H04L1/00 ,  H04Q11/00 ,  H04W88/02 ,  H04W88/08

    CPC classification number: H04L1/0059 ,  H03M13/09 ,  H03M13/23 ,  H03M13/271 ,  H03M13/276 ,  H03M13/2957 ,  H03M13/6362 ,  H03M13/6513 ,  H04L1/0045 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

    Abstract: The invention includes various embodiments for use in physical layer processing. One embodiment determines the address mapping of bits in the physical channel buffer from the address of bits in the first interleaver buffer (82). The physical channel buffer addresses (84) are determined corresponding to addresses of the bits after rate matching (88), bit scrambling (90), second interleaving (92) and physical channel mapping (94). The bits are directly read (78) from the first interleaver buffer (82) and written to the physical channel buffer (84) using the determined physical channel buffer addresses. Another embodiment determines the address mapping of bits in the first interleaver buffer (82) from the address of bits in the physical channel buffer (84). The first interleaver buffer addresses are determined corresponding to addresses of the bits after reverse rate matching (88), reverse bit scrambling (90), reverse second interleaving (92) and reverse physical channel mapping (94). The bits are directly read from the determined first interleaver buffer addresses (82) and written to the physical channel buffer addresses (84).

    Abstract translation: 本发明包括用于物理层处理的各种实施例。 一个实施例从第一交织器缓冲器（82）中的位的地址确定物理信道缓冲器中的比特的地址映射。 对应于速率匹配（88），比特加扰（90），第二交织（92）和物理信道映射（94）之后的比特的地址来确定物理信道缓冲器地址（84）。 从第一交织器缓冲器（82）直接读取这些比特（78），并使用确定的物理信道缓冲器地址将其写入物理信道缓冲器（84）。 另一实施例根据物理信道缓冲器（84）中的比特地址确定第一交织器缓冲器（82）中比特的地址映射。 对应于反向速率匹配（88），反向比特加扰（90），反向第二交织（92）和反向物理信道映射（94）之后的比特的地址来确定第一交织器缓冲器地址。 这些位从确定的第一交织器缓冲器地址（82）直接读取并写入物理信道缓冲器地址（84）。

    7.
    发明专利
    未知

    公开(公告)号：NO20034603L

    公开(公告)日：2003-12-08

    申请号：NO20034603

    申请日：2003-10-14

    Applicant: INTERDIGITAL TECH CORP

    Inventor： CASTOR DOUGLAS R ,  MCCLELLAN GEORGE W ,  MORABITO JOSEPH T

    IPC: H03M13/23 ,  H03M13/27 ,  H03M13/29 ,  H04B1/69 ,  H04B7/155 ,  H04B7/208 ,  H04B7/212 ,  H04B7/216 ,  H04B7/26 ,  H04J3/00 ,  H04J3/02 ,  H04L1/00 ,  H04Q11/00 ,  H04W88/02 ,  H04W88/08

    Abstract: The invention includes various embodiments for use in physical layer processing. One embodiment determines the address mapping of bits in the physical channel buffer from the address of bits in the first interleaver buffer. The physical channel buffer addresses are determined corresponding to addresses of the bits after rate matching, bit scrambling, second interleaving and physical channel mapping. The bits are directly read from the first interleaver buffer and written to the physical channel buffer using the determined physical channel buffer addresses. Another embodiment determines the address mapping of bits in the first interleaver buffer from the address of bits in the physical channel buffer. The first interleaver buffer addresses are determined corresponding to addresses of the bits after reverse rate matching, reverse bit scrambling, reverse second interleaving and reverse physical channel mapping. The bits are directly read from the determined first interleaver buffer addresses and written to the physical channel buffer addresses.

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