公开(公告)号：EP3000127A1

公开(公告)日：2016-03-30

申请号：EP14739997.6

申请日：2014-05-20

Applicant: Invensas Corporation

Inventor： WOYCHIK, Charles ,  UZOH, Cyprian Emeka ,  NEWMAN, Michael ,  CASKEY, Terrence ,  MONADGEMI, Pezhman

IPC: H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/32055 ,  H01L21/76802 ,  H01L21/76841 ,  H01L21/76858 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/525 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures and methods of forming the same are disclosed herein. In one embodiment, a structure can comprise a region having first and second oppositely facing surfaces. A barrier region can overlie the region. An alloy region can overlie the barrier region. The alloy region can include a first metal and one or more elements selected from the group consisting of silicon (Si), germanium (Ge), indium (Id), boron (B), arsenic (As), antimony (Sb), tellurium (Te), or cadmium (Cd).

公开(公告)号：EP3000127B1

公开(公告)日：2019-04-24

申请号：EP14739997.6

申请日：2014-05-20

Applicant: Invensas Corporation

Inventor： WOYCHIK, Charles ,  UZOH, Cyprian Emeka ,  NEWMAN, Michael ,  CASKEY, Terrence ,  MONADGEMI, Pezhman

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/532 ,  H01L23/14

公开(公告)号：EP3832706A1

公开(公告)日：2021-06-09

申请号：EP20205668.5

申请日：2013-06-06

Applicant: Invensas Corporation

Inventor： UZOH, Cyprian Emeka ,  WOYCHIK, Charles G. ,  CASKEY, Terrence ,  DESAI, Kishor V. ,  WEI, Huailiang ,  MITCHELL, Craig ,  HABA, Belgacem

IPC: H01L21/768 ,  H01L23/48 ,  H01L21/48 ,  H01L23/498 ,  H01L23/14

Abstract: A component 10 can include a substrate 20 and a conductive via 40 extending within an opening 30. The substrate 20 can have first and second opposing surfaces 21, 22. A dielectric material 60 can be exposed at an inner wall 32 of the opening 30. The conductive via 40 can define a relief channel 55 within the opening 30 adjacent the first surface 21. The relief channel 55 can have an edge 56 within a first distance D1 from the inner wall 32 in a direction D2 of a plane P parallel to and within five microns below the first surface 21, the first distance being the lesser of one micron and five percent of a maximum width of the opening 30 in the plane. The edge 56 can extend along the inner wall 32 to span at least five percent of a circumference of the inner wall.

公开(公告)号：WO2014204771A1

公开(公告)日：2014-12-24

申请号：PCT/US2014/042064

申请日：2014-06-12

Applicant: INVENSAS CORPORATION

Inventor： HABA, Belgacem ,  WOYCHIK, Charles, G. ,  UZOH, Cyprian, Emeka ,  NEWMAN, Michael ,  CASKEY, Terrence

IPC: H01L21/60 ,  H01L23/485 ,  H01L21/98 ,  H01L25/065

CPC classification number: H01L24/13 ,  H01L21/563 ,  H01L23/564 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05557 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/10145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11903 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/1319 ,  H01L2224/14517 ,  H01L2224/1601 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16104 ,  H01L2224/16105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/17505 ,  H01L2224/17517 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81001 ,  H01L2224/81007 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/8192 ,  H01L2224/83104 ,  H01L2224/9201 ,  H01L2224/9212 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00014 ,  H05K1/181 ,  H05K3/30 ,  Y10T29/4913 ,  H01L2924/00012 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2224/05552

Abstract: Microelectronic assemblies and methods for making the same are disclosed herein. In one embodiment, a method of forming a microelectronic assembly comprises: assembling first and second components (102, 128) to have first major surfaces (104, 130) of the first and second components (102, 128) facing one another and spaced apart from one another by a predetermined spacing, the first component (102) having first and second oppositely-facing major surfaces (104, 106), a first thickness extending in a first direction between the first and second major surfaces (104, 106), and a plurality of first metal connection elements (112) at the first major surface (104), the second component (128) having a plurality of second metal connection elements (132) at the first major surface (130) of the second component (128); and then plating (electroplating or electroless plating) a plurality of metal connector regions (146) each connecting and extending continuously between a respective first connection element (112) and a corresponding second connection element (132) opposite the respective first connection element (112) in the first direction. The first and second metal connection elements (112, 132) may comprise metal vias (116, 134) in the components (102, 128) or metal pads (118) at the surface of the components (102, 128), the metal vias (116, 134) or the metal pads (118) being covered by plated metal regions (114). A first seed layer (126) may be formed overlying the major surface of the first component (102) before the plating process, wherein uncovered portions of the first seed layer (126) are removed after plating the metal connector regions (146). Similarly, a second seed layer (144) may be formed overlying the major surface of the second component (128). A plurality of barrier regions (152) may overlie the sidewalls of at least one of the metal connector regions (146), the first plated metal regions (114) or the second plated metal regions. At least some corresponding first and second metal connection elements (112, 132) may optionally not share a common axis. At least some first and second surfaces (113, 131) of the first metal connection elements (112) and the respective second metal connection elements (132) connected thereto may optionally not be parallel to a common plane.

Abstract translation: 本文公开了微电子组件及其制造方法。 在一个实施例中，形成微电子组件的方法包括：组装第一和第二部件（102,128）以使第一和第二部件（102,128）彼此面对并间隔开的第一主表面（104,130） 第一部件（102）具有第一和第二相对的主表面（104,106），在第一和第二主表面（104,106）之间沿第一方向延伸的第一厚度， 以及在所述第一主表面（104）处的多个第一金属连接元件（112），所述第二部件（128）在所述第二部件的所述第一主表面（130）处具有多个第二金属连接元件（132） 128）; 然后电镀（电镀或化学镀）多个金属连接器区域（146），每个金属连接器区域在相应的第一连接元件（112）和与相应的第一连接元件（112）相对的对应的第二连接元件（132）之间连续延伸并延伸， 在第一个方向。 第一和第二金属连接元件（112,132）可以包括组件（102,128）中的金属通孔（116,134）或元件（102,128）的表面处的金属焊盘（118），金属通孔 （116,134）或金属焊盘（118）被电镀金属区域（114）覆盖。 可以在电镀工艺之前，在第一部件（102）的主表面上形成第一种子层（126），其中在镀覆金属连接器区域（146）之后，去除第一籽晶层（126）的未覆盖部分。 类似地，可以形成第二种子层（144），覆盖第二部件（128）的主表面。 多个阻挡区域（152）可以覆盖金属连接器区域（146），第一电镀金属区域（114）或第二电镀金属区域中的至少一个的侧壁。 至少一些对应的第一和第二金属连接元件（112,132）可以可选地不共享公共轴线。 第一金属连接元件（112）和连接到其上的相应的第二金属连接元件（132）的至少一些第一和第二表面（113,131）可以可选地不平行于公共平面。

公开(公告)号：WO2014152756A1

公开(公告)日：2014-09-25

申请号：PCT/US2014/027699

申请日：2014-03-14

Applicant: INVENSAS CORPORATION

Inventor： WOYCHIK, Charles ,  UZOH, Cyprian, Emeka ,  NEWMAN, Michael ,  CASKEY, Terrence

IPC: H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L27/14634 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/80 ,  H01L24/81 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/13 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/351 ,  H05K1/0298 ,  H01L2224/81 ,  H01L2924/00

Abstract: A microelectronic assembly including a dielectric region, a plurality of electrically conductive elements, an encapsulant, and a microelectronic element are provided. The encapsulant may have a coefficient of thermal expansion (CTE) no greater than twice a CTE associated with at least one of the dielectric region or the microelectronic element.

Abstract translation: 提供了包括电介质区域，多个导电元件，密封剂和微电子元件的微电子组件。 密封剂可以具有不大于与电介质区域或微电子元件中的至少一个相关联的CTE的两倍的热膨胀系数（CTE）。

公开(公告)号：WO2014107301A1

公开(公告)日：2014-07-10

申请号：PCT/US2013/075672

申请日：2013-12-17

Applicant: INVENSAS CORPORATION

Inventor： HABA, Belgacem ,  MOHAMMED, Ilyas ,  CASKEY, Terrence ,  CO, Reynaldo ,  CHAU, Ellis

IPC: H01L23/498 ,  H01L25/10 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H05K1/11 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/528 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/10126 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1191 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13101 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14135 ,  H01L2224/16105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/32225 ,  H01L2224/45012 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45101 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45624 ,  H01L2224/45655 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15322 ,  H01L2924/181 ,  H01L2924/19107 ,  H05K1/0298 ,  H05K1/181 ,  H05K1/185 ,  H05K2201/10515 ,  H05K2201/10977 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: A structure (10) may include bond elements (24) having bases joined to conductive elements (18) at a first portion of a first surface and end surfaces remote from the substrate (12). A dielectric encapsulation element (40) may overlie and extend from the first portion and fill spaces between the bond elements (24) to separate the bond elements (24) from one another. The encapsulation element (40) has a third surface facing away from the first surface. Unencapsulated portions of the bond elements (24) are defined by at least portions of the end surfaces uncovered by the encapsulation element at the third surface. The encapsulation element (40) at least partially defines a second portion (210) of the first surface that is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element (602). Some conductive elements (18) are at the second portion and configured for connection with such microelectronic element (602).

Abstract translation: 结构（10）可以包括在第一表面的第一部分和远离基底（12）的端表面处具有连接到导电元件（18）的基底的结合元件（24）。 电介质封装元件（40）可以从第一部分覆盖并延伸并填充接合元件（24）之间的空间，以将接合元件（24）彼此分离。 封装元件（40）具有背离第一表面的第三表面。 粘合元件（24）的未封装的部分由在第三表面处被封装元件未覆盖的端面的至少一部分限定。 封装元件（40）至少部分地限定第一表面的除第一部分之外的第二部分（210），并且具有尺寸适于容纳微电子元件（602）的整个区域的区域。 一些导电元件（18）位于第二部分并被配置为与这种微电子元件（602）连接。

公开(公告)号：WO2014100186A2

公开(公告)日：2014-06-26

申请号：PCT/US2013/076137

申请日：2013-12-18

Applicant: INVENSAS CORPORATION

Inventor： UZOH, Cyprian, Emeka ,  MONADGEMI, Pezhman ,  NEWMAN, Michael ,  WOYCHIK, Charles, G. ,  CASKEY, Terrence

IPC: H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/31053 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/768 ,  H01L21/76841 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/481 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2924/0002 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Methods of forming a microelectronic assembly and the resulting structures and devices are disclosed herein. In one embodiment, a method of forming a microelectronic assembly includes removing material exposed at portions of a surface of a substrate to form a processed substrate having a plurality of thinned portions separated by integral supporting portions of the processed substrate having a thickness greater than a thickness of the thinned portions, at least some of the thinned portions including a plurality of electrically conductive interconnects extending in a direction of the thicknesses of the thinned portions and exposed at the surface; and removing the supporting portions of the substrate to sever the substrate into a plurality of individual thinned portions, at least some individual thinned portions including the interconnects.

Abstract translation: 本文公开了形成微电子组件以及所得到的结构和器件的方法。 在一个实施例中，一种形成微电子组件的方法包括：去除在衬底的表面的一部分处暴露的材料，以形成经处理的衬底，该衬底具有由经处理的衬底的整体支撑部分分隔的多个减薄部分，该整体支撑部分的厚度大于厚度 所述变薄部分中的至少一些包括多个导电互连，所述导电互连在所述变薄部分的厚度的方向上延伸并且在所述表面处暴露; 以及移除衬底的支撑部分以将衬底切割成多个单独的薄化部分，至少一些单独的薄化部分包括互连。

公开(公告)号：WO2013059297A1

公开(公告)日：2013-04-25

申请号：PCT/US2012/060585

申请日：2012-10-17

Applicant: INVENSAS CORPORATION

Inventor： CASKEY, Terrence ,  MOHAMMED, Ilyas

IPC: H01L25/10 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L25/18 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3185 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/117 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06155 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/14131 ,  H01L2224/27334 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48145 ,  H01L2224/4824 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73217 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/852 ,  H01L2224/92144 ,  H01L2224/92147 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06596 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1076 ,  H01L2225/1082 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/186 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A microelectronic package (10) may include a first microelectronic unit (12) including a semiconductor chip (16A) having first chip contacts (28), an encapsulant (30) contacting an edge of the semiconductor chip, and first unit contacts (42) exposed at a surface of the encapsulant (30) and electrically connected with the first chip contacts (28). The package (10) may include a second microelectronic unit (14) including a semiconductor chip (16C) having second chip contacts (28C) at a surface thereof, and an encapsulant (54) contacting an edge of the chip of the second unit (14) and having a surface extending away from the edge. The surfaces of the chip (16C) and the encapsulant (54) of the second unit (14) define a face of the second unit. Package terminals (76) at the face may be electrically connected with the first unit contacts (42) through bond wires (100) electrically connected with the first unit contacts (42), and the second chip contacts (28C) through metallized vias (72) and traces (74) formed in contact with the second chip contacts (28C).

Abstract translation: 微电子封装（10）可以包括第一微电子单元（12），其包括具有第一芯片触点（28）的半导体芯片（16A），与半导体芯片的边缘接触的密封剂（30）和第一单元触点（42） 暴露在密封剂（30）的表面处并与第一芯片触头（28）电连接。 封装（10）可以包括第二微电子单元（14），其包括在其表面具有第二芯片触点（28C）的半导体芯片（16C）和与第二单元的芯片的边缘接触的密封剂（54） 并且具有远离边缘延伸的表面。 芯片（16C）和第二单元（14）的密封剂（54）的表面限定第二单元的面。 面上的封装端子（76）可以通过与第一单元触点（42）电连接的接合线（100）和第二芯片触点（28C）穿过金属化通孔（72）与第一单元触点（42）电连接 ）和与第二芯片触点（28C）接触形成的迹线（74）。

公开(公告)号：EP2859582A2

公开(公告)日：2015-04-15

申请号：EP13783123.6

申请日：2013-06-06

Applicant: Invensas Corporation

Inventor： UZOH, Cyprian Emeka ,  WOYCHIK, Charles G. ,  CASKEY, Terrence ,  DESAI, Kishor V. ,  WEI, Huailiang ,  MITCHELL, Craig ,  HABA, Belgacem

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L23/34 ,  H01L21/76841 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/1134 ,  H01L2224/1147 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/13565 ,  H01L2224/32105 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/81805

Abstract: A component can include a substrate and a conductive via extending within an opening in the substrate. The substrate can have first and second opposing surfaces. The opening can extend from the first surface towards the second surface and can have an inner wall extending away from the first surface. A dielectric material can be exposed at the inner wall. The conductive via can define a relief channel within the opening adjacent the first surface. The relief channel can have an edge within a first distance from the inner wall in a direction of a plane parallel to and within five microns below the first surface, the first distance being the lesser of one micron and five percent of a maximum width of the opening in the plane. The edge can extend along the inner wall to span at least five percent of a circumference of the inner wall.

公开(公告)号：WO2014022780A1

公开(公告)日：2014-02-06

申请号：PCT/US2013/053437

申请日：2013-08-02

Applicant: INVENSAS CORPORATION

Inventor： CASKEY, Terrence ,  MOHAMMED, Ilyas ,  UZOH, Cyprian, Emeka ,  WOYCHIK, Charles ,  NEWMAN, Michael ,  MONADGEMI, Pezhman ,  CO, Reynaldo ,  CHAU, Ellis ,  HABA, Belgacem

IPC: H01L23/48 ,  H01L23/12

CPC classification number: H01L25/105 ,  H01L21/486 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/02379 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45664 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/381 ,  H05K1/0298 ,  H05K3/46 ,  Y10T29/49126 ,  Y10T29/49162 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds.

Abstract translation: 制造插入件的方法包括形成结合到第一元件的一个或多个第一表面的多个引线键合。 形成电介质封装，其接触将引线接合部彼此分隔开的引线接合的边缘表面。 进一步的处理包括去除第一元件的至少一部分，其中插入件具有通过至少封装相互隔开的第一和第二相对侧，并且插入件分别在第一和第二相对侧具有第一接触和第二接触， 分别与第一和第二部件电连接，第一触点通过引线键与第二触点电连接。