公开(公告)号：JPS6180866A

公开(公告)日：1986-04-24

申请号：JP12641085

申请日：1985-06-12

Applicant: Ibm

Inventor： KASOLD JEFFREY PATRICK ,  LAM CHUNG HON

IPC: F15B5/00 ,  G11C16/04 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/7882

公开(公告)号：DE3586766T2

公开(公告)日：1993-04-22

申请号：DE3586766

申请日：1985-08-06

Applicant: IBM

Inventor： KASOLD JEFFREY PATRICK ,  LAM CHUNG HON

IPC: F15B5/00 ,  G11C16/04 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/60

Abstract: A non-volatile storage cell uses two different areas (28A, 28B) for electron injection, allowing direct overwriting of previously stored data without an intervening erase cycle. A floating gate FET has duel programming gates (PG1, PG2) disposed on its floating gate (22). Each programming gate (PG1, PG2) includes a layer (28A, 28B) of dual electron injector structure (DEIS) and a polysilicon electrode (30, 32). When writing a "0", one of the programming gates PG1, PG2) removes charge from the floating gate (22). When writing "1", the other programming gate injects charge into the floating gate (22). This charge transfer does not take place if the previously stored logic state and the logic state to be written in are identical.

公开(公告)号：DE3586766D1

公开(公告)日：1992-11-26

申请号：DE3586766

申请日：1985-08-06

Applicant: IBM

Inventor： KASOLD JEFFREY PATRICK ,  LAM CHUNG HON

IPC: F15B5/00 ,  G11C16/04 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/60

Abstract: A non-volatile storage cell uses two different areas (28A, 28B) for electron injection, allowing direct overwriting of previously stored data without an intervening erase cycle. A floating gate FET has duel programming gates (PG1, PG2) disposed on its floating gate (22). Each programming gate (PG1, PG2) includes a layer (28A, 28B) of dual electron injector structure (DEIS) and a polysilicon electrode (30, 32). When writing a "0", one of the programming gates PG1, PG2) removes charge from the floating gate (22). When writing "1", the other programming gate injects charge into the floating gate (22). This charge transfer does not take place if the previously stored logic state and the logic state to be written in are identical.

公开(公告)号：DE3174014D1

公开(公告)日：1986-04-10

申请号：DE3174014

申请日：1981-12-03

Applicant: IBM

Inventor： BAKEMAN PAUL EVANS ,  FORTINO ANDRES GUILLERMO ,  GEIPEL HENRY JOHN ,  KASOLD JEFFREY PATRICK ,  QUINN ROBERT MICHAEL

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/08 ,  H01L29/78