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    METHOD OF MAKING COMPLEMENTARY METAL OXIDE SEMICONDUCTOR STRUCTURES
    3.
    发明专利
    METHOD OF MAKING COMPLEMENTARY METAL OXIDE SEMICONDUCTOR STRUCTURES 未知

    公开(公告)号：DE3371264D1

    公开(公告)日：1987-06-04

    申请号：DE3371264

    申请日：1983-10-11

    Applicant: IBM

    Inventor： COTTRELL PETER EDWIN ,  GEIPEL HENRY JOHN ,  KENNEY DONALD MCALPINE

    IPC: H01L27/08 ,  H01L21/00 ,  H01L21/76 ,  H01L21/762 ,  H01L21/82 ,  H01L21/8238 ,  H01L29/78

    Abstract: A simple process is provided for making a planar CMOS structure wherein isolation regions required by bulk CMOS structures are first formed, an N channel device field region is self-aligned to an N well region in a semiconductor substrate and a refractory material is twice defined for forming P and N channels, the first definition masking P channel source and drain regions while defining the N channel and the second definition defining the P channel while using a photoresist layer to mask the N channel. In the process, a technique which uses a single mask level defines the well region and self-aligns the necessary field doping to the well region to provide closely spaced N and P channel devices.

    METHOD OF MAKING INTEGRATED CIRCUIT IGFET DEVICES
    5.
    发明专利
    METHOD OF MAKING INTEGRATED CIRCUIT IGFET DEVICES 未知

    公开(公告)号：DE3168523D1

    公开(公告)日：1985-03-07

    申请号：DE3168523

    申请日：1981-10-20

    Applicant: IBM

    Inventor： GEIPEL HENRY JOHN ,  SHASTEEN RICHARD BRUCE

    IPC: H01L29/78 ,  H01L21/033 ,  H01L21/265 ,  H01L21/324 ,  H01L29/08 ,  H01L21/76

    Abstract: A method for forming shallow low leakage ion implanted source/drain regions in an integrated circuit environment including semirecessed oxide isolation regions in which high parasitic device threshold voltages are provided by an oxidizing/annealing post implant process. Arsenic ions are implanted into a recessed oxide isolated substrate followed by a wet oxidation process and a non-oxidizing annealing process for a period of time to provide a passivating dielectric over low leakage source/drain regions of less than one micron junction depth and to provide adequate high temperature annealing to reduce the charge effects in the oxide isolation regions caused by the implanted arsenic ions.

    METHOD OF FABRICATING A CONDUCTIVE METAL SILICIDE STRUCTURE
    7.
    发明专利
    METHOD OF FABRICATING A CONDUCTIVE METAL SILICIDE STRUCTURE 未知

    公开(公告)号：DE3277482D1

    公开(公告)日：1987-11-19

    申请号：DE3277482

    申请日：1982-07-13

    Applicant: IBM

    Inventor： GEIPEL HENRY JOHN ,  NESBIT LARRY ALAN

    IPC: H01L29/78 ,  H01L21/027 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/768 ,  H01L23/52 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L21/285 ,  H01L21/90

    Abstract: A method of fabricating a silicide structure includes depositing a metal, e.g., molybdenum or tungsten, directly onto a thin insulating layer (12) of silicon dioxide and/or silicon nitride formed on a semiconductor substrate (10), co-depositing the metal and silicon onto the metal layer (20) and then depositing silicon (24) onto the co-deposited metal-silicon layer (22). This structure is annealed at a temperature sufficient to form a metal silicide between the thin insulating layer (12) and the layer of silicon (24). The silicon layer (24) serves as a source of silicon for the metal layer (20) which is consumed during the annealing step to form, along with the co-deposited metal-silicon layer (22), a relatively thick metal silicide layer directly on the thin silicon dioxide layer (12). A sufficiently thick silicon layer (24) is initially provided on the codeposited metal-silicon layer (22) so that a portion of the initial silicon layer remains after the annealing step has been completed. This excess silicon may be oxidized to form a passivating layer on top of the thick metal silicide layer.

    METHOD OF MAKING COMPLEMENTARY TRANSISTOR METAL OXIDE SEMICONDUCTOR STRUCTURES
    8.
    发明专利
    METHOD OF MAKING COMPLEMENTARY TRANSISTOR METAL OXIDE SEMICONDUCTOR STRUCTURES 未知

    公开(公告)号：DE3372150D1

    公开(公告)日：1987-07-23

    申请号：DE3372150

    申请日：1983-10-21

    Applicant: IBM

    Inventor： GEIPEL HENRY JOHN ,  TROUTMAN RONALD ROY ,  WURSTHORN JOHN MICHAEL

    IPC: H01L27/08 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/49 ,  H01L29/78 ,  H01L21/82

    Abstract: A process is provided which forms a bulk CMOS structure by initially depositing an oxidation barrier layer (38) on an N type semiconductor substrate (12), which is finally used as gate dielectric, forming a P well (22) in the substrate (12) through a given segment of the barrier layer (38), removing a first segment of the barrier layer to form N+ regions (26, 28) for N channel source and drain, removing a second segment of the barrier layer (38) to form a P+ field region (51, 48), removing a third segment of the barrier layer (38) to form P+ regions (60, 62) for source and drain of a P channel device, forming a first control electrode (68) having a given work function for the P channel device which acts as an ion barrier and then forming a second control electrode (70) between the N channel source and drain regions having a work function different from that of the first control electrode.

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